Yoh, A Day & Zimmermann Company · 3 hours ago
ASIC Design Verification Engineer – Risc V and/or Systolic Array experience required
United States
Contract
Remote
Senior Level
$80/hr - $120/hr
7+ years expYoh, A Day & Zimmermann Company is seeking a Senior ASIC Design Verification Engineer responsible for verifying critical blocks in an inference chiplet that enable efficient execution of AI models. The role focuses on systolic array–based compute architectures, ensuring correctness, performance, and scalability across hierarchical designs.
Bookkeeping and PayrollConsultingStaffing Agency
Hiring Manager
Jamie Gross
Responsibilities
Lead comprehensive verification planning and execution for systolic array compute blocks and full-chip designs , ensuring robust validation across all design hierarchies
Collaborate cross-functionally with architecture, firmware, and design teams to develop detailed test plans that validate systolic dataflow, compute behavior, and control logic against specifications and requirements
Design and implement advanced testbenches featuring constrained-random stimulus generation, intelligent checkers, comprehensive scoreboards, and targeted assertions to ensure correctness of array-level computation, data movement, and synchronization
Architect and execute verification strategies encompassing test planning, coverage analysis, automated regression management, and data-driven insights to maximize verification efficiency and quality for high-throughput compute architectures
Drive verification excellence through established methodologies including structured code reviews, agile sprint planning, and systematic feature deployment processes
Innovate verification approaches by researching and implementing next-generation methodologies, automated flows, and emerging technologies, including AI-driven verification tools and performance-aware validation techniques
Qualification
Required
7–10+ years of hands-on verification experience spanning test plan development, simulation environment creation, test implementation, and complex debugging across diverse IP blocks, SoCs, and system-level designs
Demonstrated proficiency in systolic array or accelerator-class compute block verification, including validation of dataflow, pipeline behavior, and scalability at array and chip levels
Advanced skills in SystemVerilog/Verilog, UVM methodology, and C/C++ programming, including embedded code development and validation for RISC V-based or accelerator control processors
Established track record in creating scalable verification flows, implementing coverage-driven verification strategies, and developing assertion-based verification frameworks for compute-intensive architectures
Benefits
Medical, Prescription, Dental & Vision Benefits (for employees working 20+ hours per week)
Health Savings Account (HSA) (for employees working 20+ hours per week)
Life & Disability Insurance (for employees working 20+ hours per week)
MetLife Voluntary Benefits
Employee Assistance Program (EAP)
401K Retirement Savings Plan
Direct Deposit & weekly epayroll
Referral Bonus Programs
Certification and training opportunities
Company
Yoh, A Day & Zimmermann Company
At Yoh, we focus on helping you precisely navigate and fulfill your talent demands.
1001-5000 employees
H1B Sponsorship
Yoh, A Day & Zimmermann Company has a track record of offering H1B sponsorships. Please note that this does not
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Funding
Current Stage
Late StageLeadership Team
Peter Melomo
Vice President, Sales Strategy & Professional Consulting Services
Tom Enright
VP Recruiting - Specialty Practices
Recent News
Philadelphia Business Journal
2025-01-11
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