Astera Labs · 5 hours ago
Senior Silicon Memory Validation Engineer
San Jose, CA
Full-time
Onsite
Mid, Senior Level
$135K/yr - $165K/yr
3+ years expAstera Labs is a provider of rack-scale AI infrastructure through purpose-built connectivity solutions. They are seeking a Senior Silicon Memory Validation Engineer to develop and execute electrical validation tests, automate IC testing, and ensure product compliance with customer requirements.
Artificial Intelligence (AI)SemiconductorElectronicsAutomotiveIntelligent Systems
Responsibilities
Develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions
Formulate a comprehensive post-Silicon validation plan
Automate the testing of ICs and board products
Design experiments to root-cause unexpected behavior
Report results and specification compliance
Work with key internal customers to quantify margins and ensure robustness
Qualification
Required
Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor's is required, and a Master's is preferred
+ 3 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision
Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!
Proven track record solving problems independently
Familiarity with DDR4/5 memory standards and DIMM configuration, experience in system testing, characterization, margin analysis and optimization
Working knowledge of key, high-speed design blocks such as PLL's, DFE, Tx EQ
Strong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration
Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis
Proficiency using high-speed lab equipment such as BERT, Oscilloscope/high-speed probe, and VNA
Preferred
Hands-on experience with signal integrity, especially as it relates to multi-rank DDR and DDR termination schemes
Working knowledge of C or C++ for embedded FW
Familiarity with PCIe/CXL compliance standards and ability to drive electrical compliance testing at industry workshops
Experience working with DRAM memory vendors on DDR4 or DDR5 to identify issues and working with internal SoC HW/FW teams to improve memory calibration and tuning sequences
Working knowledge of common serial data specifications such as I3C, I2C, SPI, etc
Knowledge of memory subsystem compliance and RAS is a plus
Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc
Knowledge of simulation tools such as MATLAB, Keysight ADS, PLTS for data analysis and modeling of signal integrity issues
Company
Astera Labs
Astera Labs is a semiconductor company that provides connectivity solutions for intelligent systems.
201-500 employees
H1B Sponsorship
Astera Labs has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (50)
2024 (44)
2023 (17)
2022 (26)
2021 (14)
2020 (7)
Funding
Current Stage
Public CompanyTotal Funding
$206.35MKey Investors
Fidelity
2024-03-20IPO
2022-11-17Series D· $150M
2021-09-27Series C· $50M
Leadership Team
Jitendra Mohan
CEO
Casey Morrison
Chief Product Officer, Co-Founder
Recent News
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2026-02-12
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