Marvell Technology · 4 hours ago
Senior Principal Engineer- SOC RTL Design
Tippecanoe County, IN
Full-time
Onsite
Senior Level, Lead/Staff
18+ years expMarvell Technology is a leading provider of semiconductor solutions that power data infrastructure across various domains. They are seeking a Senior Principal Engineer to define subsystem architecture and engage in the design and verification of complex SoCs, ensuring optimal performance and collaboration across teams.
Telecom & CommunicationsSemiconductorManufacturingInternet of ThingsDSPWireless
No H1B
U.S. Citizen Only
Responsibilities
Define the sub system architecture, micro-architecture and register specification for highly complex SoCs. Drive and participate in specification writeup
Conduct detailed performance, architectural and design requirement reviews with cross-functional teams, IP Vendors and customers
Implement a specification using RTL coding techniques and best practices
Work with third party vendors to define customization requirements of third party IPs
Work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff
Work with the verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation and emulation, performance and power analysis and debug
Help develop and/or evaluate design and verification methodologies and participate in improving existing ones
Collaborate with and provide guidance to the post silicon and software teams for silicon bring up and performance tuning
Provide mentorship to the more junior team members
Qualification
Required
Bachelor's degree in Computer Science, Electrical Engineering or related fields and 20+ years of related professional experience
Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 18+ years of experience
Experience in creating architectural, micro-architectural, and register specifications
Verilog/System Verilog RTL coding with System Verilog assertions
Well-versed in all stages of the ASIC design flow (including specification, architecture and design implementation, prototype bring-up)
Has worked on complex IP or ARM or RISC V based Processor Subsystem Design
Understanding on Caliptra and Hardware Security Standards is required
Experience with scripting in Perl/Python/Shell
Preferred
Expertise in any of the following domains would be a big plus: networking, embedded systems architecture, computer architecture, machine learning accelerators
Benefits
Competitive compensation
Great benefits
Company
Marvell Technology
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology.
5001-10000 employees
Funding
Current Stage
Public CompanyTotal Funding
unknown2017-01-20Post Ipo Equity
2016-05-13Post Ipo Equity
2015-02-05Acquired
Leadership Team
Matthew Murphy
Chairman and CEO
Radha Nagarajan
SVP & CTO, Optical Engineering
Recent News
2026-02-03
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2026-02-02
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