eTeam · 19 hours ago
Design Verification Engineer
eTeam is seeking a Design Verification Engineer to own the verification of FPGA designs used in high-end router products. The role involves creating test plans, developing verification environments, and collaborating with design engineers to ensure successful design verification.
Responsibilities
Own verification of entire FPGA design used in high end router products
Understand the design specification and interact with design engineers to identify verification scenarios
Create test plan, constrained-random verification environment, testcases, regressions and coverage reports
Identify and write all types of coverage measures for stimulus and corner-cases
Qualification
Required
Strong academic background in Electrical Engineering (Bachelor's required, Master's preferred)
7-10 years of pure verification experience in ASIC/FPGAs
Proficient in SystemVerilog with clear OOP concepts
Experience developing object-oriented testbench infrastructure, BFMs, testcases in UVM
Experience with PCIe, Ethernet, slow speed interfaces like I2C, SPI, MDIO etc
Understanding of verifying IP integrations, strategies, corner cases etc
Ability to independently develop test plans, test sequences, generate stimuli, and collaborate with RTL designers to debug failures
Proficiency with industry-standard tools, revision control systems, and regression systems
Preferred
Master's degree in Electrical Engineering
Experience with scripting language like Perl, Python is a plus
Company
eTeam
eTeam is a staffing agency that also provides payrolling services.
H1B Sponsorship
eTeam has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (36)
2024 (205)
2023 (11)
2022 (7)
2021 (24)
2020 (25)
Funding
Current Stage
Late StageTotal Funding
unknown2023-12-04Acquired
Recent News
2025-11-19
2025-08-21
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