Axiom Global Technologies · 1 day ago
Analog Layout Engineer
Axiom Global Technologies is seeking a Senior Analog Layout Engineer to lead the physical design and layout of high-performance, high-speed CMOS integrated circuits. This role involves driving full-custom IC layout in advanced foundry technologies while ensuring optimal performance, reliability, and manufacturability.
ConsultingLogisticsInformation TechnologyDelivery
Responsibilities
Lead full-custom layout of high-performance, high-speed analog and mixed-signal CMOS circuits
Design and implement layouts for advanced technology nodes ( 3nm, 5nm, 7nm, 16nm ) in leading foundry processes
Apply advanced layout techniques including device matching, common-centroid, interdigitation, symmetry, shielding, and guard rings
Optimize layouts for performance, area, power, signal integrity, and yield
Perform and resolve DRC, LVS, ERC, and antenna violations using industry-standard verification tools
Conduct parasitic extraction (PEX) and support post-layout simulation and timing/performance closure
Address layout-dependent effects (LDE), EM/IR, reliability, and variation challenges in advanced nodes
Collaborate closely with circuit designers, verification teams, and process engineers to meet design specifications
Drive layout reviews, enforce industry best practices , and support tape-out activities
Mentor junior layout engineers and contribute to layout methodologies and design guidelines
Qualification
Required
Bachelor's or Master's degree in Electrical/Electronics Engineering or related field
6+ years of experience in analog/mixed-signal full-custom layout
Proven experience working in advanced CMOS nodes (16nm and below)
Strong hands-on experience with Cadence Virtuoso Layout Suite
Strong hands-on experience with Calibre / Pegasus / Assura for physical verification
Deep understanding of analog layout techniques and matching strategies
Deep understanding of high-speed layout considerations and signal integrity
Deep understanding of parasitic effects, LDE, and process variations
Deep understanding of foundry PDKs and design rules