Senior Layout Engineer jobs in United States
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Arm · 1 day ago

Senior Layout Engineer

Arm is a leading company in semiconductor technology, and they are seeking a highly skilled Senior Layout Engineer to develop innovative custom standard cells. The role involves collaborating with circuit designers and physical design teams to produce high-quality layouts that meet aggressive performance, power, and area targets while influencing methodologies and shaping the quality of pioneering silicon.

SemiconductorBig DataElectronicsSoftwareInternet of ThingsAnalytics
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Growth Opportunities
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H1B Sponsor Likelynote

Responsibilities

Create, optimize , and verify custom digital standard cell layouts, realizing advanced IP in the latest process technologies
Work within the Solutions Engineering Group on custom cell development, and customer-specific design solutions
Collaborate with circuit design and implementation teams to ensure performance, usability, reliability, and alignment with PDK constraints
Develop and/or aid in layout methodologies, automation scripts, and standard processes to improve productivity and consistency
Conduct full physical verification including DRC, LVS, ERC, and support resolution of verification issues
Drive continuous improvement in cell architecture, design rules understanding, and layout quality for next-generation processes

Qualification

Cadence VirtuosoMask/Layout DesignDRCLVS VerificationSemiconductor Device PhysicsDesign-for-ManufacturabilityScripting for AutomationCross-team CollaborationCommunication Skills

Required

Associate's degree in Electrical Engineering, Microelectronics, related field or experience
5+ years of hands-on mask/layout design experience in semiconductor or ASIC development
Expert proficiency with Cadence Virtuoso and deep experience with advanced layout techniques
Experience building or enhancing standard cell libraries or high-performance custom circuits
Familiarity with EM/IR, reliability constraints, and design-for-manufacturability (DFM) practices
Strong understanding of semiconductor device physics, PDK constraints, and layout-dependent effects (LDE)
Proven experience performing DRC, LVS and handling signoff-quality verification flows. Interpretation of reports and debugging
Experience designing in advanced nodes (5nm and below)
Ability to interpret schematics, floorplans, and design constraints and translate them into optimized layouts
Strategically plan and develop layouts with an eye towards maximum reuse across multiple architectures
Excellent communication and cross-team collaboration skills

Preferred

Familiarity with scripting for layout automation (e.g., SKILL, Tcl, Python) is highly desirable
Background working directly with process engineering teams or supporting early-node technology enablement
Beyond basic user knowledge of additional EDA tools such as Calibre, Assura, Pegasus, or similar

Company

Arm’s foundational technology is defining the future of computing. A future built by the greatest technology ecosystem in the world.

H1B Sponsorship

Arm has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (295)
2024 (166)
2023 (164)
2022 (123)
2021 (103)
2020 (133)

Funding

Current Stage
Public Company
Total Funding
unknown
2016-07-18Acquired
1999-01-15IPO

Leadership Team

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Rene Haas
Chief Executive Officer
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Jason Child
EVP and Chief Financial Officer
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Company data provided by crunchbase