Butterfly Network, Inc. · 14 hours ago
Staff Engineer, Digital ASIC Design
California, United States
Full-time
Hybrid
Lead/Staff
$175K/yr - $175K/yr
8+ years expButterfly Network, Inc. is leading a digital revolution in medical imaging with its proprietary Ultrasound-on-Chip™ technology. The Staff Engineer in Digital ASIC Design will be responsible for digital IC/ASIC design, owning RTL implementations, and collaborating with cross-functional teams to drive functional closures and support tapeout processes.
Artificial Intelligence (AI)ElectronicsHealth CareManufacturingMedical DeviceSemiconductor
No H1B
Responsibilities
Proven ownership of a defined digital IP/subsystem from micro-architecture and RTL implementation through verification closure and tapeout support
Strong RTL skills in SystemVerilog/Verilog, including pipelined datapaths, control logic/state machines, and high-throughput streaming interfaces
Experience designing sustained high-throughput datapaths, including buffering/FIFOs, arbitration/backpressure, bandwidth budgeting, and SRAM/memory interface considerations
Strong understanding of silicon-level design constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and PPA tradeoffs
Effective collaboration with verification to drive functional closure through signoff (SV/UVM and/or Python-based frameworks such as cocotb)
Experience building and using bit-accurate reference models (e.g., Python) to validate fixed-point behavior and enable end-to-end checking
Experience supporting post-silicon bring-up/debug and silicon correlation, partnering with firmware/validation to root-cause issues and deliver fixes
Strong cross-functional communication to close hardware–firmware interfaces (register maps, control/status paths, data-plane contracts) with systems/firmware stakeholders
Experience implementing compute-intensive DSP pipelines (e.g., beamforming, filtering, noise reduction, MAC-heavy datapaths) with fixed-point design discipline
Exposure to ultrasound / medical imaging systems or sensor data acquisition pipelines and image-quality KPIs
Advanced-node experience (28nm or smaller), including timing sensitivity and third-party IP integration
Qualification
Required
BS/MS/PhD in EE/CE (or equivalent practical silicon design experience)
8+ years (typical Staff level) in digital IC / ASIC / SoC design with substantial hands-on RTL ownership and at least one major-IP or full-chip tapeout cycle
Proven ownership of a defined digital IP/subsystem from micro-architecture and RTL implementation through verification closure and tapeout support
Strong RTL skills in SystemVerilog/Verilog, including pipelined datapaths, control logic/state machines, and high-throughput streaming interfaces
Experience designing sustained high-throughput datapaths, including buffering/FIFOs, arbitration/backpressure, bandwidth budgeting, and SRAM/memory interface considerations
Strong understanding of silicon-level design constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and PPA tradeoffs
Effective collaboration with verification to drive functional closure through signoff (SV/UVM and/or Python-based frameworks such as cocotb)
Experience building and using bit-accurate reference models (e.g., Python) to validate fixed-point behavior and enable end-to-end checking
Experience supporting post-silicon bring-up/debug and silicon correlation, partnering with firmware/validation to root-cause issues and deliver fixes
Strong cross-functional communication to close hardware–firmware interfaces (register maps, control/status paths, data-plane contracts) with systems/firmware stakeholders
Preferred
Experience implementing compute-intensive DSP pipelines (e.g., beamforming, filtering, noise reduction, MAC-heavy datapaths) with fixed-point design discipline
Exposure to ultrasound / medical imaging systems or sensor data acquisition pipelines and image-quality KPIs
Advanced-node experience (28nm or smaller), including timing sensitivity and third-party IP integration
Experience integrating programmable compute subsystems (MPU/accelerator), including control interfaces and memory/bandwidth tradeoffs
Benefits
Comprehensive health insurance, encompassing dental and vision coverage, is provided to all our employees.
We also contribute to Health Savings Account (HSA) accounts for all enrolled employees on an annual basis.
Comprehensive Employee Assistance Program - we provide access to tools and resources to support your emotional health and day-to-day needs.
401k plan and match - we facilitate your retirement goals.
Eligible employees will have the opportunity to participate in Employee Stock Purchase Plan (ESPP)
Unlimited Paid Time Off + 10 Holiday Days a Year - recharge and come back ready to make an impact
Parental Leave - we aim to provide our employees with time to bond with their growing family, along with additional support for primary caregivers to help transition back to work
Competitive salaried compensation - we value our employees and show it
Equity - we want every employee to be a stakeholder
The opportunity to build a revolutionary healthcare product and save millions of lives!
Company
Butterfly Network, Inc.
Butterfly’s mission is to democratize healthcare by making medical imaging accessible to everyone, everywhere.
51-200 employees
Funding
Current Stage
Public CompanyTotal Funding
$605.6MKey Investors
Bill & Melinda Gates FoundationFidelity
2025-01-29Post Ipo Equity· $75.6M
2022-03-09Grant· $5M
2021-02-16Post Ipo Equity· $175M
Leadership Team
Joseph DeVivo
President, Chief Executive Officer
Nevada Sanchez
Co-Founder, VP of ASIC Design
Recent News
2026-01-16
2026-01-16
Company data provided by crunchbase