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Canvendor · 6 hours ago

Physical Design Engineer

Texas, United States

Contract

Onsite

Senior Level

5+ years exp

Canvendor is seeking an experienced Physical Design Engineer with 5–10+ years of hands-on experience in ASIC physical design. The candidate will be responsible for end-to-end block/full-chip physical design activities from RTL2GDSII/Netlist2GDSII, ensuring high-quality layouts and verification processes.

AnalyticsAppsManagement Consulting

H1B Sponsor Likely

Responsibilities

Drive full-chip SoC/Block level physical design from RTL2GDSII/Netlist2GDSII

Perform top-level/sub-system/Block synthesis, floor planning, partitioning, and hierarchical integration

Develop and implement full-chip/Block level power planning and power grid strategies

Manage block integration, timing budgeting, and interface closure

Execute and optimize placement, CTS, routing, and post-route flows at full-chip level

Lead full-chiptiming closure across MMMC scenarios

Handle top-level congestion, SI, noise, IR drop, and EM closure

Perform and drive physical verification closure (DRC/LVS/ERC/ANTENNA)

Manage ECO flows including full-chip and block-level ECOs

Collaborate closely with RTL, synthesis, STA, DFT, packaging, and verification teams

Support tapeout planning, signoff checks, and final delivery milestones

Build and enhance automation scripts and PD flows

Qualification

ASIC physical designFull-chip SoC implementationTiming closurePower planningCadence InnovusSynopsys ICC2PrimeTimeTcl scriptingPython scriptingShell scriptingDebugging skillsProblem-solving skillsCommunication skillsCross-team collaboration

Required

5–10+ years of hands-on experience in ASIC physical design

Experience in full-chip SoC implementation

Deep expertise in top-level floorplanning and partitioning

Deep expertise in chip-level power planning and multi-voltage domains

Deep expertise in hierarchical and flat implementation flows

Deep expertise in timing budgeting and interface timing closure

Deep expertise in CTS and clock architecture at SoC level

Deep expertise in congestion and routing optimization

Strong knowledge of MMMC timing setup and closure

Strong knowledge of OCV/AOCV/POCV, SI and Crosstalk analysis

Strong knowledge of multi-voltage and low-power flows (UPF/CPF)

Strong knowledge of IR/EM and thermal considerations

Hands-on experience with Cadence Innovus / Synopsys ICC2

Hands-on experience with PrimeTime / Tempus

Hands-on experience with Voltus / RedHawk

Hands-on experience with Calibre / Pegasus

B.E./B.Tech/M.E./M.Tech in Electronics / VLSI / Electrical Engineering or related field

Preferred

Experience in advanced nodes (≤16nm / 7nm / 5nm preferred)

Exposure to large SoC designs with multiple clock and power domains

Experience handling high-speed interfaces and hard macros

Knowledge of packaging interactions and bump/IO planning

Strong Tcl scripting skills; Python/Shell scripting is a plus

Experience mentoring engineers and leading PD closure tasks

Experience mentoring junior engineers (preferred for senior candidates)

Company

Canvendor

Canvendor is an IT firm that offers analytics, supply chain, business consulting and application development services to various industries.

Founded in 2015

San Jose, California, USA

51-200 employees

http://www.canvendor.com/

H1B Sponsorship

Canvendor has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)

Distribution of Different Job Fields Receiving Sponsorship

Represents job field similar to this job

Trends of Total Sponsorships

2025 (3)

2023 (2)

2022 (3)

Funding

Current Stage

Growth Stage

Leadership Team

Prabal Bhadauriya

Client Partner, Operations and Business Strategy

Company data provided by crunchbase