Senior TPU RTL Design Engineer, Networking, Inter-Chip Interconnects jobs in United States
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Google · 22 hours ago

Senior TPU RTL Design Engineer, Networking, Inter-Chip Interconnects

Google is a leading technology company that is shaping the future of AI/ML hardware acceleration. The role involves driving cutting-edge TPU technology and designing custom silicon solutions that power Google's AI/ML applications, with a focus on high-speed interconnect subsystems and ASIC/SoC hardware design.

AppsArtificial Intelligence (AI)Cloud StorageSearch EngineSEO
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Growth Opportunities
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H1B Sponsor Likelynote

Responsibilities

Lead the microarchitecture and RTL execution to deliver high-performance network design components which meet strict Power, Performance and Area (PPA) goals and satisfy established coding and quality guidelines
Collaborate with system architects and software/firmaware teams to ensure alignment between system and IP requirements
Own the complete RTL lifecycle from initial microarchitecture, coding and documentation to ensuring sign-off readiness for Lint, CDC, and synthesis
Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness
Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements

Qualification

ASIC designRTL designNetworking IPIEEE networking standardsScripting languagesDigital design fundamentalsTeam collaborationProblem-solving

Required

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
5 years of experience in high-performance ASIC design
Experience developing networking IP across one or more layers, such as the Media Access Control (MAC), Link (L2), or Physical (PHY) layers
Experience architecting or designing RTL solutions for digital systems
Experience with high-speed interconnects

Preferred

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
7 years of experience in high-performance ASIC design
Experience with IEEE networking standards and applications
Experience with scripting languages (e.g., Tcl, Python or Perl)
Familiarity with one or more industry-standard tools for CDC, RDC, RTL Linting, or LEC
Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols

Benefits

Bonus
Equity
Benefits

Company

Google specializes in internet-related services and products, including search, advertising, and software. It is a sub-organization of Alphabet.

H1B Sponsorship

Google has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (8763)
2024 (8872)
2023 (9682)
2022 (11626)
2021 (9109)
2020 (9785)

Funding

Current Stage
Public Company
Total Funding
$26.1M
Key Investors
Kleiner Perkins,Sequoia CapitalAndy Bechtolsheim
2004-08-19IPO
1999-06-07Series Unknown· $25M
1998-11-01Angel· $1M

Leadership Team

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Sundar Pichai
CEO
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Thomas Kurian
CEO - Google Cloud
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Company data provided by crunchbase