Altera · 3 hours ago
Physical Design Technical Lead/Engineer
San Jose, California, United States
Full-time
Onsite
Senior Level, Lead/Staff
$143K/yr - $206K/yr
10+ years expAltera provides leadership programmable solutions that are easy to use and deploy, enabling limitless possibilities for AI. As a Sr. Physical Design Technical Lead/Engineer, you will play a critical role in backend implementation flow for FPGA/SoC devices, collaborating with various teams to achieve performance, power, and area goals.
Enterprise SoftwareManufacturingSemiconductorSoftware
Responsibilities
Lead and execute physical design implementation tasks (floorplanning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist to GDSII
Apply PPA optimization techniques (performance / timing closure, power reduction, area efficiency) across blocks or full-chip hierarchies
Collaborate with front-end design, architecture, CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets and DFT Insertions are met
Develop and improve physical design flows, methodologies, scripts and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR and reduce manual intervention
Participate in timing, power, EM/IR integrity, signal/power noise, DRC/LVS/ERC verification and sign-off readiness
Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domains for programmable regulation, and yield optimization
Work closely with manufacturing and packaging partners to ensure implementation is manufacturable (DFM/DFY), meets yield targets and meets high-volume production requirements
Debug physical design issues, interact with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds. Mentor and collaborate with junior engineers; contribute to reviews, documentation of flows, and continuous process improvement
Qualification
Required
Bachelor's in Electrical Engineering, Computer Engineering or related field with 10+ years of experience in the following skills:
Hands-on experience in digital/SoC physical design (synthesis through P&R through sign‐off)
Experience with industry‐standard EDA tools (e.g., Synopsys IC Compiler/ Fusion, Cadence Innovus/Encounter, PrimeTime, STAR-RCX, Calibre) for high speed digital ASIC/SoC implementation
Scripting/programming experience (TCL, Python, Perl, shell) for flow automation and productivity enhancement
Physical design flow experience: floor-planning, CTS, placement, routing, gating power domains, clock domain crossing, multi-power domain design, timing closure, ECOs, DRC/LVS/DFM issues
Experience in power/IR analysis, signal/power integrity reports, and propose corrective actions
Experience interfacing with front-end teams (RTL, architecture), CAD/EDA tool teams, manufacturing and packaging teams
Preferred
Primetime (Tempus)
Fusion Compiler (ICC/ICC2/Innovus)
Calibre
Conformal (Formality)
Redhawk (Voltus)
Tetramax/Tessent
Company
Altera
Altera provides programmable logic devices and design software for various applications. It is a sub-organization of Intel.
1001-5000 employees
H1B Sponsorship
Altera has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (67)
Funding
Current Stage
Public CompanyTotal Funding
unknown2025-04-14Acquired
1988-03-31IPO
Leadership Team
Raghib Hussain
Chief Executive Officer
Recent News
Business Wire
2025-11-25
2025-11-19
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