Broadcom · 16 hours ago
Physical Design Engineer
San Jose, CA
Full-time
Onsite
Senior Level, Lead/Staff
$141K/yr - $226K/yr
10+ years expBroadcom is looking for a senior level RTL synthesis engineer. The role involves optimizing gate level netlists for timing, area, and power while debugging issues and collaborating with designers to resolve them.
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Responsibilities
Expert in Logic/Physical Synthesis using advanced optimization techniques and generating optimized Gate Level Netlist for Timing, Area, Power
Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them
Deep knowledge about industry standards in Physical aware synthesis
Experience in developing and implementing DFT flow
Experience with CDC, RDC, static timing analysis methodologies and relevant tools
Expert with developing automation scripts and design flow
Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failure
Perform RTL Lint and work with the Designers to create waivers
Expert in generating Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC
Analyze the inter-block timing and come up with IO budgets for the various partition blocks
Good understanding of design tape-out to foundries and solid understanding of supply chain for IC Product development
Qualification
Required
MS in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design
Expert in Logic/Physical Synthesis using advanced optimization techniques and generating optimized Gate Level Netlist for Timing, Area, Power
Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them
Deep knowledge about industry standards in Physical aware synthesis
Experience in developing and implementing DFT flow
Experience with CDC, RDC, static timing analysis methodologies and relevant tools
Expert with developing automation scripts and design flow
Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failure
Perform RTL Lint and work with the Designers to create waivers
Expert in generating Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks
Good understanding of design tape-out to foundries and solid understanding of supply chain for IC Product development
Preferred
Understanding of Cadence tools - Genus, Joules, Conformal
Understanding of Power analysis tools - Redhawk
Deep understanding of Signal Integrity and Power Integrity for High Speed designs
Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results
Excellent time and task management, and interpersonal skills
Benefits
Medical
Dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave
Vacation time
Company
Broadcom
Broadcom is a designer, developer, and global supplier of a broad range of analog and digital semiconductor connectivity solutions.
10001+ employees
H1B Sponsorship
Broadcom has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (92)
2024 (77)
2023 (79)
2022 (112)
2021 (110)
2020 (89)
Funding
Current Stage
Public CompanyTotal Funding
unknown2017-10-31Post Ipo Equity
2015-05-28Acquired
1998-04-17IPO
Leadership Team
Greg Singh
CTO for APJ, Enterprise Security Group
Kirsten Spears
CFO and CAO, Broadcom
Recent News
2026-01-25
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