Saige Partners · 22 hours ago
Design For Test Engineer
Saige Partners is seeking a Design-for-Test Engineer to test and validate next-generation chips. The role involves collaborating with Front End and Physical Design teams to implement DFT and test designs for RF and Bluetooth/Wireless LAN chipsets.
Responsibilities
Experience with memory BIST – Siemens Tessent Flow
Experience with gate-level simulation and simulation debug
Experience with automation and scripting – Tcl/Perl/Python
Experience with scan compression – SEQ/Ultra/TestKompress
Experience with ATPG – Tetramax
Experience with ATPG diagnosis, ATE debug and silicon bring up
DFT pattern translation – VTRAN
Experience with RTL design – Verilog/system Verilog
Some experience with STA and timing analysis concepts – PrimeTime (CDC, clock gating checks, timing constraints)
Qualification
Required
5+ years relevant industrial DFT experience
Excellent problem solving and debugging skills
Ability to complete assignments independently
Experience with memory BIST – Siemens Tessent Flow
Experience with gate-level simulation and simulation debug
Experience with automation and scripting – Tcl/Perl/Python
Experience with scan compression – SEQ/Ultra/TestKompress
Experience with ATPG – Tetramax
Experience with ATPG diagnosis, ATE debug and silicon bring up
DFT pattern translation – VTRAN
Experience with RTL design – Verilog/system Verilog
Some experience with STA and timing analysis concepts – PrimeTime (CDC, clock gating checks, timing constraints)
Company
Saige Partners
Saige Partners is a staffing agency that provides recruitment, advisory, and human resource services for diverse industries.
Funding
Current Stage
Early StageLeadership Team
Recent News
Corridor Business Journal
2025-07-29
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