AMD · 8 hours ago
Silicon Design Verification Engineer
San Jose, CA
Full-time
Onsite
Mid Level
$136K/yr - $204K/yrAMD is a company focused on building innovative products that enhance computing experiences across various domains. They are seeking a Design Verification Engineer to contribute to the verification of complex digital designs, collaborating with architects and design engineers to ensure high-quality technology delivery.
AI InfrastructureArtificial Intelligence (AI)Cloud ComputingComputerEmbedded SystemsGPUHardwareSemiconductor
No H1B
Responsibilities
Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
Interact with architects and design engineers to create a comprehensive verification test plan
Design testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
Debug tests with design engineers to deliver functionally correct design blocks
Identify and write coverage measures for stimulus quality improvements
Perform coverage analysis to identify verification holes and achieve closure on coverage metrics
Qualification
Required
Bachelors or Masters degree in Computer Engineering/Electrical Engineering
Passion for modern, complex processor architecture, digital design, and verification
Excellent communication skills and experience collaborating with other engineers located in different sites/time zones
Strong analytical and problem-solving skills
Willingness to learn and ready to take on problems
Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
Interact with architects and design engineers to create a comprehensive verification test plan
Design testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
Debug tests with design engineers to deliver functionally correct design blocks
Identify and write coverage measures for stimulus quality improvements
Perform coverage analysis to identify verification holes and achieve closure on coverage metrics
Preferred
Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs
Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification
Strong understanding of different phases of ASIC and/or full custom chip development
Experience in block level NOC (Net work on Chip) verification
Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics
Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs
Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques
Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management
Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan)
Benefits
AMD benefits at a glance.
Company
AMD
Advanced Micro Devices is a semiconductor company that designs and develops graphics units, processors, and media solutions.
Founded in 1969
10001+ employees
Funding
Current Stage
Public CompanyTotal Funding
unknownKey Investors
OpenAIDaniel Loeb
2025-10-06Post Ipo Equity
2023-03-02Post Ipo Equity
2021-06-29Post Ipo Equity
Leadership Team
Lisa Su
Chair & CEO
Mark Papermaster
CTO and EVP
Recent News
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