Chiparama · 17 hours ago
Principle Physical Verification Engineer
San Jose, CA
Full-time
Onsite
Lead/Staff
10+ years expChiparama is seeking a hands-on Physical Verification expert with extensive experience in top-level DRC/LVS ownership on advanced nodes. The ideal candidate will lead full-chip signoff and collaborate with Physical Design, Foundry, and EDA teams while possessing strong technical judgment and debugging skills.
Information Technology & Services
Hiring Manager
Alok Tiwari
Responsibilities
Own full-chip and block-level DRC/LVS signoff for advanced-node SoCs
Drive top-level DRC/LVS convergence using Calibre (nmDRC, nmLVS, RVE)
Integrate and debug Innovus–Calibre signoff flows
Analyze, debug, and resolve complex DRC/LVS violations at top level
Work closely with Physical Design, Timing, Power, and Packaging teams
Interface with Foundry (TSMC/Samsung/Intel) for rule interpretation and waivers
Develop and maintain runsets, scripts, and automation for signoff efficiency
Provide technical leadership and mentorship to junior engineers
Participate in tape-out execution and post-silicon debug support if required
Qualification
Required
10+ years of hands-on experience in Physical Verification / Physical Design Signoff
Strong expertise in Calibre DRC, LVS, RVE
Cadence Innovus (top-level integration and signoff flows)
Proven experience owning full-chip/top-level DRC & LVS closure
Deep understanding of advanced process nodes (7nm / 5nm / 3nm / 2nm)
Hierarchical and flat verification flows
Strong scripting skills in TCL / Perl / Python / Shell
Experience working with large, complex SoCs (CPU/GPU/AI/Networking preferred)
Excellent debugging, analytical, and problem-solving skills
Company
Chiparama
Chiparama: Your Global Partner for ASIC & SOC Design At Chiparama (www.chiparama.com), we specialize in delivering cutting-edge ASIC and SOC design solutions.
11-50 employees
Funding
Current Stage
Early StageCompany data provided by crunchbase