Altera · 4 hours ago
Physical Design Engineer
San Jose, CA
Full-time
Onsite
Mid, Senior Level
$114K/yr - $165K/yr
3+ years expAltera is a leading technology company, and they are seeking a Physical Design Engineer to play a critical role in the backend implementation flow for FPGA/SoC devices. The engineer will collaborate with various teams to achieve performance, power, and area goals, focusing on programmable logic structures and integration.
Enterprise SoftwareManufacturingSemiconductorSoftware
Responsibilities
Execute physical design implementation tasks (floorplanning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist to GDSII
Apply PPA optimization techniques (performance/timing closure, power reduction, area efficiency) across block-level and full-chip hierarchies
Collaborate with front-end design, architecture, and CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets, and DFT insertions are met
Develop and enhance physical design flows, methodologies, scripts, and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR, and reduce manual intervention
Participate in timing, power, EM/IR integrity, signal/power noise, and DRC/LVS/ERC verification for sign-off readiness
Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domains for programmable regulation, and yield optimization
Debug physical design issues and interact with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 3+ years of experience in:
Hands-on digital/SoC physical design (synthesis through P&R and sign-off)
Industry-standard EDA tools (e.g., Synopsys IC Compiler/Fusion, Cadence Innovus/Encounter, PrimeTime, STAR-RCX, Calibre) for high-speed digital ASIC/SoC implementation
Scripting/programming (TCL, Python, Perl, shell) for flow automation and productivity enhancement
Physical design flow: floorplanning, CTS, placement, routing, power domain gating, clock domain crossing, multi-power domain design, timing closure, ECOs, and DRC/LVS/DFM resolution
Power/IR analysis, signal/power integrity reporting, and corrective action planning
Interfacing with front-end teams (RTL, architecture), CAD/EDA tool teams, and manufacturing/packaging teams
Preferred
Experience with advanced process nodes (7nm, 5nm or smaller) or FPGA/programmable logic device flows
Familiarity with FPGA architecture: routing fabrics, programmable logic blocks (PLBs), on-chip networks, I/O rings, static/dynamic reconfiguration
Expertise in low-power design methodologies, power grid design, power gating, multi-voltage domain implementation, and power sign-off flows
Prior exposure to full-chip integration flows (block-to-chip convergence) and high-frequency (1 GHz+) timing closure
Experience in high-volume manufacturing environments, including yield and DFM/DFY considerations
Experience mentoring or leading small physical design sub-teams or owning major P&R blocks
Company
Altera
Altera provides programmable logic devices and design software for various applications. It is a sub-organization of Intel.
1001-5000 employees
H1B Sponsorship
Altera has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (67)
Funding
Current Stage
Public CompanyTotal Funding
unknown2025-04-14Acquired
1988-03-31IPO
Leadership Team
Raghib Hussain
Chief Executive Officer
Recent News
Business Wire
2025-11-25
2025-11-19
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