IC Package Design Engineer jobs in United States
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Claros · 3 days ago

IC Package Design Engineer

Claros is a power management solutions company that is innovating at the intersection of power and compute to make AI more sustainable and widely available. The IC Package Design Engineer will design, develop, and optimize advanced IC package substrates for high-performance semiconductor products, collaborating closely with various engineering teams to ensure robust and manufacturable package solutions.

Computer Hardware

Responsibilities

Design and route complete IC packages, including stack-up definition, signal routing, power distribution, and optimization for SI/PI performance
Analyze die floorplans, develop ball maps, perform fan-out studies, and assess routing feasibility to ensure optimal package performance and reliability
Apply knowledge of high-speed interfaces (e.g., DDR, PCIe, USB, FPGA, RGMII, GPIO) to support high-bandwidth and low-latency designs
Navigate complex design constraints and incorporate simulation and design review feedback to improve electrical and manufacturing outcomes
Perform DRC and DFM checks using tools such as Cam350, ensuring compliance with industry and foundry standards
Create accurate substrate drawings, bonding diagrams, and manufacturing deliverables using AutoCAD
Define BGA ball patterns and optimize routing in collaboration with chip and package engineers
Generate and maintain package design documentation, assembly instructions, and build sheets using Oracle PLM or equivalent systems
Support package design and assembly documentation for multiple product lines, coordinating with global operations and manufacturing teams
Work cross-functionally with IC design, system architecture, SI/PI, thermal, and package assembly teams using Cadence APD (v17.x)

Qualification

IC package layoutCadence Allegro Package DesignerSI/PI fundamentalsDFM/DRC complianceBGA packagingCam350AutoCADCommunication skillsCross-functional collaboration

Required

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
6-8 years overall experience in IC package layout and substrate design
Proficiency with Cadence Allegro Package Designer (APD)
Solid understanding of SI/PI fundamentals, stack-up design, and package-level constraints
Hands-on experience with BGA packaging, ball map creation, and full-package routing
Familiarity with DRC/DFM processes and manufacturing requirements
Experience using Cam350 and AutoCAD for layout verification and documentation
Strong communication skills and ability to work effectively with cross-functional engineering teams

Preferred

Experience supporting high-performance networking, switching, optical, or processor products
Exposure to SI/PI or thermal simulation workflows and design reviews
Familiarity with package assembly flows and global manufacturing operations
Experience working in large-scale semiconductor environments

Benefits

100% employer paid, comprehensive health care including medical, dental, and vision for you and your family.
Paid maternity and paternity for 14 weeks at employees' normal pay.
Unlimited PTO, with management approval.
Opportunities for professional development and continued learning.
Optional 401K, FSA, and equity incentives available.

Company

Claros

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Claros is a power management platform that utilizes cutting-edge hardware, software to enhance energy distribution & usage at data centers.

Funding

Current Stage
Early Stage
Total Funding
$9.7M
2025-02-27Seed· $9.7M
Company data provided by crunchbase