Apple · 1 week ago
AMS SerDes Robustness Analysis Validation Architect
San Francisco, CA
Full-time
Onsite
Senior Level, Lead/Staff
$257K/yr - $386K/yr
20+ years expApple is seeking a seasoned SerDes Robustness Analysis & Validation Architect to drive the robustness, performance, and margin validation of high-speed SerDes PHYs. This hands-on role involves architecting validation strategies, collaborating with design and system teams, and leading lab experiments to ensure efficient validation processes.
AppsArtificial Intelligence (AI)BroadcastingDigital EntertainmentFoundational AIMedia and EntertainmentMobile DevicesOperating SystemsTVWearables
Responsibilities
Define and architect margin-to-fail validation strategies to uncover weaknesses and failure conditions in high-speed SerDes PHYs across multiple process, voltage, temperature, and different system environments
Develop and implement stress-to-fail methodologies, covering end-to-end systems, such as stressing equalization paths, clocking structures, jitter sensitivities, and link training edge cases, etc
Collaborate early with SerDes design, architecture, and system teams to review specifications, define coverage priorities, and to build in needed design-for-test (DFT) insertion or sensors to improve observability, measurements, pattern generators, observability hooks, etc
Lead hands-on lab experiments to validate assumptions, isolate issues, root-cause failures, and fine-tune test coverage for both standalone IP and system-level interactions
Partner with the validation team to balance test coverage and execution time, helping shape an efficient validation pipeline that enhances risk reduction within time constraints
Analyze silicon behaviors across multiple builds and revisions; derive insights to guide validation refinement and inform design updates
Provide post-silicon feedback that improves future architectural decisions, design margins, and validation methodology
Guide junior validation engineers, share debug techniques, and contribute to internal standard processes for SerDes validation
Qualification
Required
Strong technical foundation and hands-on approach to drive the robustness, performance, and margin validation of high-speed SerDes PHYs
Deep understanding of SerDes design and validation principles, SOC/system integration, and real-world system environments
Strong collaboration with design, architecture, and system teams to ensure the IP is designed with design for testability
Hands-on lab role that requires close collaboration with designers, architects, system, and test engineers to validate next-generation SerDes IPs from design conception through production
Define and architect margin-to-fail validation strategies to uncover weaknesses and failure conditions in high-speed SerDes PHYs across multiple process, voltage, temperature, and different system environments
Develop and implement stress-to-fail methodologies, covering end-to-end systems, such as stressing equalization paths, clocking structures, jitter sensitivities, and link training edge cases
Collaborate early with SerDes design, architecture, and system teams to review specifications, define coverage priorities, and to build in needed design-for-test (DFT) insertion or sensors to improve observability
Lead hands-on lab experiments to validate assumptions, isolate issues, root-cause failures, and fine-tune test coverage for both standalone IP and system-level interactions
Partner with the validation team to balance test coverage and execution time, helping shape an efficient validation pipeline that enhances risk reduction within time constraints
Analyze silicon behaviors across multiple builds and revisions; derive insights to guide validation refinement and inform design updates
Provide post-silicon feedback that improves future architectural decisions, design margins, and validation methodology
Guide junior validation engineers, share debug techniques, and contribute to internal standard processes for SerDes validation
Preferred
PhD in Electrical Engineering or related field with 20+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug
Hands-on lab experience with lab instrumentations such as oscilloscopes, BERTs, protocol analyzers, etc, and measurement setups tailored for SerDes PHYs
Deep understanding of high-speed serial link protocols (PCIe, USB, Ethernet, DisplayPort, etc.) and equalization techniques (such as CTLE, DFE, FFE, etc.)
Strong foundation in analog/mixed-signal design principles and familiarity with signal integrity (SI) and power integrity (PI) impacts
Skilled in programming (Python, C/C++, etc.) and data analysis tools for validation automation and correlation studies
Proven ability to break down complex problems, isolate issues, and root-cause at the circuit, protocol, and system levels
Demonstrated experience in design-for-validation, including fault injection, internal monitors, and behavioral hooks
Experience validating multi-lane PHYs with adaptive EQ, clocking and CDR paths, and challenging compliance requirements in various real systems
Familiarity with production and characterization flows, including margin-to-fail and stress testing techniques
Ability to guide test coverage optimization to reduce execution time without sacrificing risk coverage
Experience providing post-silicon insights that shaped future design changes
Passion for deep debug and a 'find the flaw' mentality, with an interest to explore the unexpected
Benefits
Comprehensive medical and dental coverage
Retirement benefits
A range of discounted products and free services
Reimbursement for certain educational expenses — including tuition
Discretionary bonuses or commission payments
Relocation
Company
Apple
Apple is a technology company that designs, manufactures, and markets consumer electronics, personal computers, and software.
10001+ employees
H1B Sponsorship
Apple has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
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Funding
Current Stage
Public CompanyTotal Funding
$5.67BKey Investors
Berkshire HathawayMicrosoftSequoia Capital
2025-05-05Post Ipo Debt· $4.5B
2025-01-16Post Ipo Debt· $0.31M
2021-04-30Post Ipo Equity
Leadership Team
Tim Cook
CEO
Craig Federighi
SVP, Software Engineering
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