AMD · 8 hours ago
Senior Staff Pre‑Silicon Power Modeling Lead — x86 SoCs
Austin, TX
Full-time
Hybrid
Senior Level, Lead/Staff
$171K/yr - $257K/yr
10+ years expAMD is a company focused on building great products that accelerate next-generation computing experiences. They are seeking a Senior Staff Pre-Silicon Power Modeling Lead to own SoC-level pre-silicon power modeling, ensuring accurate power projections and robust planning to de-risk program power budgets.
AI InfrastructureArtificial Intelligence (AI)Cloud ComputingComputerEmbedded SystemsGPUHardwareSemiconductor
Responsibilities
Own the SoC power model end‑to‑end using AMD’s converged methodology, delivering accurate workload‑based power estimates for CPU/GPU/NPU, fabric/interconnect, memory, and I/O
Define use‑case power envelopes across automotive, networking, storage, industrial, and robotics segments; partner with product/marketing to derive representative workloads and KPIs
Drive DVFS/AVFS strategy (P‑states, C‑states, voltage/frequency points), telemetry requirements, and FW hand‑offs based on model outputs; provide early tables and guardrails to FW/BIOS
Establish IP/subsystem power budgets; run sensitivity studies to guide architectural decisions (e.g., cache sizes, fabric frequencies, NPU/GPU configurations)
Build repeatable model‑to‑silicon correlation plans (CaC/static/dynamic splits, EDC/TDC interactions, droop mitigation) and maintain a power scorecard for program reviews
Lead tool flows & automation (e.g., PowerArtist, PrimeTime PX; Python‑based pipelines) to ingest activity (FSDB/VCD), generate reports, and publish dashboards for stakeholders
Collaborate across Architecture, RTL/Design, Physical Design, FW/BIOS, and System PnP to ensure converged Perf/Watt outcomes from concept through bring‑up
Qualification
Required
B.S./M.S. in EE/CE/CS (or related) with 10+ years in SoC pre‑silicon power modeling/estimation and cross‑domain collaboration
Demonstrated experience building top‑level SoC power models with high correlation to silicon, including IP‑level VBM integration and workload‑based projections
Hands‑on with EDA/tooling: PowerArtist, PrimeTime PX (or equivalents), activity annotation (FSDB/VCD), UPF/CPF power intent, Python for automation
Deep knowledge of x86 micro‑architecture (CPU pipelines, caches), GPU/NPU basics, memory subsystems, interconnect/fabric behavior, and power delivery/PDN interactions
Proven ability to define DVFS/AVFS strategies and drive FW telemetry requirements; familiarity with EDC/TDC/CaC semantics and their impact on power
A validated SoC power model & scorecard that anchors program power budgets and executive reviews
Workload‑specific DVFS/AVFS tables and telemetry specs for FW/BIOS enablement
Correlation reports (estimated vs. measured) and recommendations that accelerate first‑time‑right silicon
Own the SoC power model end‑to‑end using AMD's converged methodology, delivering accurate workload‑based power estimates for CPU/GPU/NPU, fabric/interconnect, memory, and I/O
Define use‑case power envelopes across automotive, networking, storage, industrial, and robotics segments; partner with product/marketing to derive representative workloads and KPIs
Drive DVFS/AVFS strategy (P‑states, C‑states, voltage/frequency points), telemetry requirements, and FW hand‑offs based on model outputs; provide early tables and guardrails to FW/BIOS
Establish IP/subsystem power budgets; run sensitivity studies to guide architectural decisions (e.g., cache sizes, fabric frequencies, NPU/GPU configurations)
Build repeatable model‑to‑silicon correlation plans (CaC/static/dynamic splits, EDC/TDC interactions, droop mitigation) and maintain a power scorecard for program reviews
Lead tool flows & automation (e.g., PowerArtist, PrimeTime PX; Python‑based pipelines) to ingest activity (FSDB/VCD), generate reports, and publish dashboards for stakeholders
Collaborate across Architecture, RTL/Design, Physical Design, FW/BIOS, and System PnP to ensure converged Perf/Watt outcomes from concept through bring‑up
Preferred
Segment experience modeling power for automotive (AEC‑Q100/ASIL) use‑cases, networking throughput workloads, storage I/O patterns, industrial/robotics duty cycles
System performance modeling familiarity (GEM5/Simics/SystemC) to align Perf/Watt predictions and bottleneck analysis with architecture teams
Experience creating PnP dashboards/regressions (Python/Jenkins/Grafana/InfluxDB) for continuous tracking
Benefits
AMD benefits at a glance.
Company
AMD
Advanced Micro Devices is a semiconductor company that designs and develops graphics units, processors, and media solutions.
10001+ employees
H1B Sponsorship
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Funding
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unknownKey Investors
OpenAIDaniel Loeb
2025-10-06Post Ipo Equity
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Leadership Team
Lisa Su
Chair & CEO
Mark Papermaster
CTO and EVP
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