Apple · 3 days ago
PHY Design Verification Engineer
Apple is seeking a PHY Design Verification Engineer to join their growing wireless silicon development team. In this role, you will be responsible for pre-silicon RTL verification of wireless PHY and its interfaces, working closely with various engineering teams to ensure high design quality.
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Responsibilities
Work closely with the system and design teams to review and understand the PHY subsystem microarchitecture, and create verification plans from specifications, review and refine to achieve coverage targets
Build block/subsystem level test benches with a reference model, using the best-in-class DV methodology. Architect test benches with maximum reusability in mind
Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found
Create and analyze block/subsystem-level coverage models, and add test cases to increase coverage
Use machine learning and AI technologies to identify design and test bench issues and ensure DV quality
Support PHY subsystem validation using Palladium and/or FPGA
Work with team members to improve DV methodology and flow
Qualification
Required
Pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC
Interact with DV methodologists, designers, and communication systems engineers to develop reusable test bench and verification environment deploying the latest methodology with metric-driven verification
Work closely with the system and design teams to review and understand the PHY subsystem microarchitecture, and create verification plans from specifications, review and refine to achieve coverage targets
Build block/subsystem level test benches with a reference model, using the best-in-class DV methodology
Architect test benches with maximum reusability in mind
Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found
Create and analyze block/subsystem-level coverage models, and add test cases to increase coverage
Use machine learning and AI technologies to identify design and test bench issues and ensure DV quality
Support PHY subsystem validation using Palladium and/or FPGA
Work with team members to improve DV methodology and flow
Preferred
Verification experience of wireless/wired communication block/subsystem
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion
Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage
Experience of using Matlab/C reference model and bit-accurate verification
Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee
Proficient in shell and Python scripting, Perl scripting
Experience of using AI technologies in data mining/analysis
Experience of Palladium/FPGA validation
Should be a team player with excellent communication skills, self-motivated and well organized
Benefits
Comprehensive medical and dental coverage
Retirement benefits
A range of discounted products and free services
Reimbursement for certain educational expenses — including tuition
Discretionary bonuses or commission payments
Relocation
Company
Apple
Apple is a technology company that designs, manufactures, and markets consumer electronics, personal computers, and software.
H1B Sponsorship
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Funding
Current Stage
Public CompanyTotal Funding
$5.67BKey Investors
Berkshire HathawayMicrosoftSequoia Capital
2025-05-05Post Ipo Debt· $4.5B
2025-01-16Post Ipo Debt· $0.31M
2021-04-30Post Ipo Equity
Leadership Team
Tim Cook
CEO
Craig Federighi
SVP, Software Engineering
Recent News
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