Apple · 1 hour ago
Cellular SoC Static Timing Analysis Engineer
San Diego, CA
Full-time
Onsite
Mid Level
$140K/yr - $258K/yr
3+ years expApple is a leading technology company known for its innovative products and services. They are seeking a Cellular SoC Static Timing Analysis Engineer to be part of their modem team, responsible for ensuring timing closure in chip design and collaborating with multi-functional teams to resolve timing issues.
AppsArtificial Intelligence (AI)BroadcastingDigital EntertainmentFoundational AIMedia and EntertainmentMobile DevicesOperating SystemsTVWearables
Responsibilities
Full chip and block level timing closure ownership throughout the entire project
Generation of block and full chip timing constraints
Own timing sign-off to make sure timing requirements are met across all corners, modes, and conditions
Work closely with various multi-functional teams on resolving sophisticated timing issues for major building blocks of sophisticated SoCs
Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications
Qualification
Required
BS and 3+ years of relevant industry experience
Hands-on experience in ASIC timing constraints generation and timing closure
Good knowledge in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing
Good understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and BIST testing
Own STA sign-off for block and chip level including custom timing checks
Hands on experience in timing/SDC constraints generation and management
Knowledge of low-power techniques including clock gating, power gating and multi-voltage designs
Proficient in scripting languages (Tcl and Perl/Python)
Strong communication skills are a pre-requisite as the candidate will collaborate with a lot of different groups (e.g. digital design, DFT, physical design, etc.)
Preferred
MS and 3+ years of relevant industry experience
Strong background in Constraint analysis and debug, using industry standard tools such as Synopsys CA (Constraint Analyzer)
Understand and implement improving existing methodologies and flows
Experience in reducing the number of timing signoff corners by merging different timing modes is highly desired
Solid understanding of timing corners/modes, process variations and signal integrity related issues
Benefits
Comprehensive medical and dental coverage
Retirement benefits
A range of discounted products and free services
Reimbursement for certain educational expenses — including tuition
Discretionary bonuses or commission payments
Relocation
Company
Apple
Apple is a technology company that designs, manufactures, and markets consumer electronics, personal computers, and software.
10001+ employees
H1B Sponsorship
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Funding
Current Stage
Public CompanyTotal Funding
$5.67BKey Investors
Berkshire HathawayMicrosoftSequoia Capital
2025-05-05Post Ipo Debt· $4.5B
2025-01-16Post Ipo Debt· $0.31M
2021-04-30Post Ipo Equity
Leadership Team
Tim Cook
CEO
Craig Federighi
SVP, Software Engineering
Recent News
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2025-09-25
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