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AMD · 2 days ago

High-Speed Analog/Mixed-Signal Design Engineer

San Jose, CA

Full-time

Onsite

Senior Level

$157K/yr - $236K/yr

AMD is a company dedicated to building innovative products that enhance next-generation computing experiences across various domains including AI and data centers. They are seeking a High-Speed Analog/Mixed-Signal Design Engineer to be part of their analog/mixed signal IP design team, responsible for designing and developing high-speed memory and PHY IP solutions.

AI InfrastructureArtificial Intelligence (AI)Cloud ComputingComputerEmbedded SystemsGPUHardwareSemiconductor

Growth Opportunities

No H1B

Responsibilities

Definition, review and sign-off on IP top level and component level specifications

AMS components circuit and layout design

Supervise pre-silicon layout, post-silicon characterization and debug

Support product bring-up and debug , and Sign-off on test-plans and characterization reports

Interface with SOC teams, system HW/SW teams, and global manufacturing teams

Qualification

Mixed signal designHigh-speed PHY designCircuit simulation toolsLow power design techniquesFinFET CMOS processCommunication skillsTeam collaborationInitiativeOwnership

Required

Experience leading others in technical settings

Excellent communication, writing, and presentation skills

Definition, review and sign-off on IP top level and component level specifications

AMS components circuit and layout design

Supervise pre-silicon layout, post-silicon characterization and debug

Support product bring-up and debug, and Sign-off on test-plans and characterization reports

Interface with SOC teams, system HW/SW teams, and global manufacturing teams

BS, MS or PhD in Electrical Engineering, Computer Engineering or related equivalent

Preferred

Experience in high speed serial and/or parallel mixed signal PHY/IO designs

Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for receiver/transmitter and PLL/DLL/clocking

Hand-on design experience in multi-Gbps serial (PCIE, USB, …), parallel high BW memory interface PHY/IOs (DDR4/DDR5, HBM2/HBM3, gDDR5/gDDR6, …) and chip-to-chip links PHY IPs such as UCIe

Experience in mixed signal design circuit blocks such as digital/analog DLLs, duty cycle corrector, clock and data recovery, clock mixer, …

Experience in low power design techniques for high speed/custom digital circuit (e.g. CMOS/CML high speed design for counters, dividers, …) design and analysis including transistor level timing sign-off

Solid understanding of power, area and performance trade-offs in mixed signal IP design

Design Experience in FinFet advanced CMOS process nodes 7nm and below coupled with a solid understanding of transistor device performance and fundamentals

Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools

Work with project-manager, system architects, IC designers and physical designers to guarantee quality/timely deliverables meeting project's schedule and technical requirements

Track record of successfully taking designs to production

Excellent written and verbal communication skills able to operate without direct supervision but also work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic/fast paste environment

Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge