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Northrop Grumman · 1 day ago

Principal / Senior Principal FPGA/ASIC Verification Engineer - R10218288-2

Jessup, MD

Full-time

Onsite

Senior Level, Lead/Staff

$120K/yr - $179K/yr

5+ years exp

Northrop Grumman is a leading global provider of secure software-defined, hardware enabled mission systems. They are seeking digital verification engineers to develop full-custom digital and mixed signal circuits, requiring proficiency in HDL and HVL, as well as familiarity with a coverage-driven verification methodology.

AerospaceData IntegrationManufacturingRemote SensingSecurity

Growth Opportunities

No H1B

Security Clearance Required

U.S. Citizen Only

Responsibilities

Must be proficient in HDL (VHDL/Verilog) and HVL (SystemVerilog)

Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology (UVM) is required

Successful candidates will have familiarity with a coverage-driven verification methodology from planning through closure as well as knowledge of industry standard interfaces

Experience with object-oriented programming languages and concepts is also required

Must have strong written and oral communication skills

Qualification

HDL (VHDL/Verilog)HVL (SystemVerilog)Universal Verification Methodology (UVM)FPGAASICScripting languagesLinux OSCoverage-driven verificationIndustry standard interfacesObject-oriented programmingCommunication skills

Required

Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 5 years of relevant experience (3 years with technical MS; 0 years with PhD) - Experience in HDL (VHDL/Verilog) and HVL (SystemVerilog)

Experience with FPGA or ASIC

Knowledge of Universal Verification Methodology (UVM)

Experience with scripting languages (Bash, Perl, Python, Tcl)

Familiarity with Linux OS

Familiarity with a coverage driven verification methodology from planning through closure

Knowledge of industry standard interfaces

Experience with object-oriented programming languages and concepts

Must be a US Citizen and must have or be able to obtain and maintain a Top Secret/SCI security clearance with Polygraph

Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 8 years of relevant experience (6 years with technical MS; 3 years with PhD) - Experience in HDL (VHDL/Verilog) and HVL (SystemVerilog)