Intel Corporation · 1 day ago
Si TD memory Quality and Reliability Engineer
US, California, Santa Clara
Full-time
Hybrid
Mid, Senior Level
$181K/yr - $298K/yr
3+ years expIntel Corporation is a leader in semiconductor manufacturing, focusing on innovative quality and reliability solutions. The Senior TD Memory Quality and Reliability Engineer will lead technical efforts to ensure the quality and reliability of memory arrays and IP, focusing on technology certification, process validation, and product lifecycle management.
Semiconductors
Responsibilities
Lead technology Vccmin and/or fuse certification efforts to meet the needs of both internal and foundry customers
Investigate and understand reliability failure mechanisms and the underlying physics
Analyze test chip Vccmin and/or fuse data to identify trends and potential issues, providing feedback to the process on conversion decisions and driving processes to meet certification requirements
Characterize SRAM memory bit cell margin and noise; perform Sil2Sim for product design guidance. Characterize fuse programming and read margin
Develop and enhance statistical modeling methods for Vccmin reliability. Engage and lead effort in Cert method definition/update for Vccmin/fuse
Collaborate with cross-functional teams to ensure quality and reliability standards are met throughout the product lifecycle
Communicate project status, technical findings, and recommendations to stakeholders, including process/LYA, device, design, and customers
Drive continuous improvement initiatives to enhance quality and reliability processes and methodologies
Provide technical leadership and mentorship to junior engineers and team members
Qualification
Required
Ph.D. in Electrical Engineering, Material Science, Physics, or a related field, with 3+ years of relevant experience in semiconductor device physics and data analysis
Masters in Electrical Engineering, Material Science, Physics, or a related field, with 6+ years of relevant experience in semiconductor device physics and data analysis
Proficient in using JMP
Demonstrated knowledge of memory array design and testing
Experience in quality and reliability methods and modeling
Preferred
Proficiency in scripting languages such as Python or JSL
Experience in statistical modeling
Benefits
Competitive pay
Stock
Bonuses
Health
Retirement
Vacation
Company
Intel Corporation
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside.
10001+ employees
H1B Sponsorship
Intel Corporation has a track record of offering H1B sponsorships. Please note that this does not
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Funding
Current Stage
Late StageLeadership Team
Brea Watts, MFA
Communications Manager, CEO
Carol Bartz
CEO
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