SEAKR · 1 day ago
Senior Verification Engineer
SEAKR Engineering is a leading-edge provider of advanced electronics for space applications, seeking a Verification Engineer to develop verification and simulation strategies. The role involves constructing simulation environments, conducting design reviews, and leading a team to verify complex devices.
AerospaceData ManagementHardwareManufacturingMechanical EngineeringSecuritySoftware Engineering
Responsibilities
The Engineer is responsible for the construction and maintenance of simulation environments using System Verilog with UVM (Universal Verification Methodology), and performing and evaluating regression tests for a design under test
The candidate must be able to extract and derive test requirements and sequences for an interface or interfaces based on available design documentation and requirements
Ability to architect and construct full test environments for complex devices using UVM, including coverage, is required
The candidate shall be capable of diagnosing sophisticated test failures and filing results, and be capable of analyzing code coverage to adjust agent sequence behavior
Ability to provide direction to less senior verification engineers is required
Ability to lead a team of verification engineers to fully verify a device is required
Ability to use simulation tools such as Mentor Graphics Modelsim/Questasim for simulation debug and reporting is required
Ability to analyze Verilog RTL to diagnose test failures is required
Ability to analyze VHDL is a plus
Must be able to work effectively under pressure to meet tight deadlines
Experience verifying Ethernet and PCIe designs a plus
Experience using/integrating verification IP into existing environments a plus
Experience verifying DSP related designs a plus
Qualification
Required
A Bachelors degree in Electrical Engineering or Computer Science
A minimum of 10 years of verification engineering experience
Ability to architect and construct full test environments for complex devices using UVM, including coverage
Ability to provide direction to less senior verification engineers
Ability to lead a team of verification engineers to fully verify a device
Ability to use simulation tools such as Mentor Graphics Modelsim/Questasim for simulation debug and reporting
Ability to analyze Verilog RTL to diagnose test failures
Must be able to work effectively under pressure to meet tight deadlines
Preferred
A Master's Degree
Ability to analyze VHDL
Experience verifying Ethernet and PCIe designs
Experience using/integrating verification IP into existing environments
Experience verifying DSP related designs
Benefits
Rich medical, dental and vision insurance plans
Generous 401(k) retirement plan
Year-end bonus
Variety of paid leave, such as vacation, sick, bereavement, and FMLA
Company
SEAKR
SEAKR, a wholly owned subsidiary of RTX, is a Leading-Edge Provider of Advanced Space Electronics Solutions.
Funding
Current Stage
Growth StageTotal Funding
unknown2021-09-14Acquired
Leadership Team
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2024-04-14
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