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Samsung Ads · 5 months ago

SoC Architect, Memory Subsystem (Principal Engineer)

3655 N 1st St, San Jose, CA, USA

Full-time

Onsite

Lead/Staff

$217K/yr - $360K/yr

13+ years exp

Samsung, a world leader in advanced semiconductor technology, is seeking a SoC Architect for the Memory Subsystem at their Austin Research and Development Center. In this senior technical lead role, you will define SoC memory architectures for next-generation mobile products, focusing on innovative solutions and performance modeling.

Marketing & Advertising

Responsibilities

Drive the definition of SoC memory and cache subsystems for next-generation mobile products with a heavy focus on supporting On-Device ML

Identify and analyze emerging use cases, as well as, proposing new and innovative SoC memory architectures to efficiently support them

Perform high-level performance modeling and analysis of hardware features, applications, benchmarks, and complex uses cases

Analyze the impact of system-level architectural trade-offs (including CPU, GPU, NPU, ISP, memory subsystems, and system software)

Create necessary simulation/analysis tools to evaluate complex memory subsystem use cases such as gaming and camera use cases

Deliver architecture proposals and specifications to the design team

Drive cross-company collaboration by communicating and articulating architecture proposals clearly and effectively

Qualification

Architecture analysisPerformance modelingMemory subsystem designCache subsystemsSimulation capabilitiesInterconnect protocolsHigh performance designAndroid EcosystemArm ArchitectureCommunication skills

Required

15+ years of experience with a Bachelor's Degree in Computer Science/Engineering, or 13+ years of experience with a Master's Degree, or 11+ years of experience with a PhD

Extensive experience in architecture analysis and performance modeling, ranging from simple analytical models to complex cycle accurate performance model and correlation, especially around CPU – memory subsystems

High proficiency in leveraging existing simulation capabilities or create new simulation capabilities where necessary

Detailed knowledge of cache subsystems including caching policies and understanding the tradeoffs of latency, bandwidth and hierarchies

Detailed knowledge of memory subsystem design to include existing/emerging JEDEC memory standards

Strong written and verbal communication skills

Knowledge of high performance, high efficiency design