Butterfly Network, Inc. · 13 hours ago
Distinguished Engineer, ASIC
New York, NY
Full-time
Hybrid
Lead/Staff
$240K/yr - $240K/yr
8+ years expButterfly Network, Inc. is leading a digital revolution in medical imaging with its innovative Ultrasound-on-Chip™ technology. They are seeking a Distinguished Engineer, ASIC to take ownership of complex digital IC subsystems, from architecture to tapeout, while collaborating cross-functionally to meet chip-level requirements.
Artificial Intelligence (AI)ElectronicsHealth CareManufacturingMedical DeviceSemiconductor
Responsibilities
BS/MS/PhD in EE/CE/CS or equivalent practical tapeout experience
8–12+ years (typical Principal level) in digital IC / ASIC / SoC design with significant hands-on RTL ownership
Strong understanding of digital IC implementation at the silicon level, including timing closure implications, clock/reset domain architecture, power-aware design, and PPA (power, performance, area) tradeoffs
Proven ability to own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design
Strong RTL skills in SystemVerilog/Verilog to implement silicon-proven digital architectures, including pipelined datapaths, control logic, state machines, and high-throughput streaming interfaces
Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design
Prior work at advanced technology nodes (28nm or smaller), including timing closure challenges and integration of third-party IP
Experience collaborating with verification teams to validate complex digital architectures and resolve functional issues through tapeout signoff
Comfortable working cross-functionally with analog, systems, and packaging/board teams to close chip-level requirements and integration details, including hardware–firmware interfaces (register maps, control/status paths, data-plane contracts)
Experience implementing compute-intensive digital pipelines (e.g., DSP, beamforming, AI, or MAC-heavy/vector datapaths)
Exposure to medical imaging / ultrasound systems, beamforming pipelines, or sensor data acquisition architectures
Experience designing or integrating programmable digital compute blocks (e.g., AI accelerators, MPUs, or eFPGA fabrics), including instruction/control interfaces, memory hierarchy, data movement, and PPA tradeoffs
Qualification
Required
BS/MS/PhD in EE/CE/CS or equivalent practical tapeout experience
8–12+ years (typical Principal level) in digital IC / ASIC / SoC design with significant hands-on RTL ownership
Strong understanding of digital IC implementation at the silicon level, including timing closure implications, clock/reset domain architecture, power-aware design, and PPA (power, performance, area) tradeoffs
Proven ability to own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design
Strong RTL skills in SystemVerilog/Verilog to implement silicon-proven digital architectures, including pipelined datapaths, control logic, state machines, and high-throughput streaming interfaces
Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design
Prior work at advanced technology nodes (28nm or smaller), including timing closure challenges and integration of third-party IP
Experience collaborating with verification teams to validate complex digital architectures and resolve functional issues through tapeout signoff
Comfortable working cross-functionally with analog, systems, and packaging/board teams to close chip-level requirements and integration details, including hardware–firmware interfaces (register maps, control/status paths, data-plane contracts)
Preferred
Experience implementing compute-intensive digital pipelines (e.g., DSP, beamforming, AI, or MAC-heavy/vector datapaths)
Exposure to medical imaging / ultrasound systems, beamforming pipelines, or sensor data acquisition architectures
Experience designing or integrating programmable digital compute blocks (e.g., AI accelerators, MPUs, or eFPGA fabrics), including instruction/control interfaces, memory hierarchy, data movement, and PPA tradeoffs
Benefits
Comprehensive health insurance, encompassing dental and vision coverage, is provided to all our employees.
Comprehensive Employee Assistance Program - we provide access to tools and resources to support your emotional health and day-to-day needs.
401k plan and match - we facilitate your retirement goals.
Eligible employees will have the opportunity to participate in Employee Stock Purchase Plan (ESPP)
Unlimited Paid Time Off + 10 Holiday Days a Year - recharge and come back ready to make an impact
Parental Leave - we aim to provide our employees with time to bond with their growing family, along with additional support for primary caregivers to help transition back to work
Competitive salaried compensation - we value our employees and show it
Equity - we want every employee to be a stakeholder
The opportunity to build a revolutionary healthcare product and save millions of lives!
Company
Butterfly Network, Inc.
Butterfly’s mission is to democratize healthcare by making medical imaging accessible to everyone, everywhere.
51-200 employees
H1B Sponsorship
Butterfly Network, Inc. has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2023 (1)
2022 (2)
2021 (9)
2020 (4)
Funding
Current Stage
Public CompanyTotal Funding
$605.6MKey Investors
Bill & Melinda Gates FoundationFidelity
2025-01-29Post Ipo Equity· $75.6M
2022-03-09Grant· $5M
2021-02-16Post Ipo Equity· $175M
Leadership Team
Joseph DeVivo
President, Chief Executive Officer & Chairman of the Board
Nevada Sanchez
Co-Founder, VP of ASIC Design
Recent News
2025-12-11
GlobeNewswire
2025-12-08
2025-11-21
Company data provided by crunchbase