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zeroRISC · 1 month ago

SoC/ASIC Design Verification Engineer

Boston, MA

Full-time

Hybrid

Mid Level

4+ years exp

zeroRISC is redefining chip security and supply chain integrity by empowering device owners and operators in crucial sectors. The SoC/ASIC Design Verification Engineer will develop, verify, and maintain silicon in security-sensitive settings, ensuring functionality and performance throughout the chip design life cycle.

HardwareInformation TechnologySecurity

Responsibilities

Verify ASIC/SoC functionality, performance, security, and power throughout the full chip design life cycle, from test plan definition to sign-off

Build high quality verification environments at the chip/top and block levels following engineering best practices

Write thorough verification documentation including test plans

Diagnose, debug, and resolve regression failures and other errors

Achieve coverage closure

Ensure design functionality while upholding stringent timelines in collaboration with architecture, design, software, system, and silicon validation teams as well as engineering program managers

Qualification

UVMSystemVerilogSimulation-based verificationTestbenches developmentFormal verificationPythonElectrical EngineeringComputer ScienceLow power design verificationSecurity ASICs knowledgeComputer architecture knowledge

Required

Bachelor's degree in Electrical Engineering or Computer Science, or a related technical field or equivalent experience

4 years of experience with simulation-based verification methodologies and languages such as UVM and SystemVerilog or formal verification-based techniques including industry standard tools

Experience developing and maintaining testbenches, test cases, and verification environments for simulation-based verification or formal verification environments