ASML · 1 day ago
Design Verification Engineer
San Diego, CA
Full-time
Onsite
Mid, Senior Level
$106K/yr - $178K/yr
2+ years expASML is seeking a Design Verification Engineer to lead the verification strategy for complex FPGA designs. The role involves architecting advanced verification environments, ensuring design integrity, and mentoring junior engineers.
CommercialElectronicsHardwareIndustrialIndustrial ManufacturingMachinery ManufacturingManufacturingNanotechnologySemiconductorSoftware
Responsibilities
Define and own verification strategy for large-scale, multi-block FPGA systems
Architect and implement advanced, reusable verification environments using SystemVerilog UVM and UVMF
Develop sophisticated test benches, constrained-random tests, and coverage models to achieve full functional and code coverage
Drive requirement traceability and compliance through robust documentation and reporting
Collaborate with architects, design engineers, and cross-functional teams to ensure design integrity and verification completeness
Lead debug efforts for complex system-level issues and root-cause analysis
Establish and enforce best practices for verification methodology, automation, and regression management
Mentor and guide junior and mid-level engineers; provide technical leadership and training
Influence tool adoption, methodology improvements, and process optimization across the organization
Other duties as assigned
Qualification
Required
Bachelors' degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields
2+ years' experience with a Bachelor's degree
0 + years' experience with a Master's degree
Understanding of coverage-driven verification, constrained-random methodologies, and assertion-based verification
Experience with UVM for modular and reusable verification IP development
Familiarity with CI/CD pipelines, version control systems (Git), and continuous integration frameworks
Must possess industry experience in FPGA design verification; equivalent experience in ASIC workflows acceptable
Proven track record of leading verification for complex SoC or FPGA systems, including hardware bring-up and test
Expert-level proficiency in SystemVerilog UVM, including architecting environments and building custom components from scratch
Extensive experience with simulation tools (e.g., QuestaSim, VCS, or similar) and regression management
Strong understanding of coverage-driven verification, constrained-random methodologies, and assertion-based verification
Deep experience with UVM for modular and reusable verification IP development
Familiarity with CI/CD pipelines, version control systems (Git), and continuous integration frameworks
Ability to architect and optimize complex verification environments for scalability and reuse
Advanced problem-solving and debugging skills for system-level and multi-block designs
Strong leadership and mentoring capabilities; able to guide teams and influence technical direction
Excellent communication and collaboration skills for cross-functional engagement
Expertise in coverage analysis and closure strategies
Strong organizational and planning skills for managing large verification projects
Experience driving methodology improvements and automation initiatives
Familiarity with FPGA-specific verification strategies and hardware validation
Ability to innovate and implement process enhancements for efficiency and quality
Preferred
Proficiency in scripting languages (Python, Perl, or similar) for automation and flow optimization
Experience with UVMF for modular and reusable verification environments
Exposure to formal verification techniques and advanced debug methodologies
Benefits
Medical, dental, vision, and basic life insurance
401k plan
Eight (8) hours of vacation leave every month
(13) paid holidays throughout the calendar year
Company
ASML
ASML is a manufacturer of chip-making equipment.
10001+ employees
H1B Sponsorship
ASML has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
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Trends of Total Sponsorships
2025 (460)
2024 (354)
2023 (538)
2022 (443)
2021 (196)
2020 (279)
Funding
Current Stage
Public CompanyTotal Funding
$526.46M2022-05-10Post Ipo Debt· $526.46M
1995-03-24IPO
Leadership Team
Christophe Fouquet
President and Chief Executive Officer
Marco Pieters
Chief Technology Officer
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