Grafton Sciences · 2 days ago
Senior Toolchain Engineer, Firmware
San Francisco, CA
Full-time
Onsite
Senior LevelGrafton Sciences is building AI systems with general physical ability, aiming to push the frontier of physical AI. The role involves designing and implementing automation systems for generating firmware and HDL, ensuring digital design correctness, and collaborating with various teams to integrate these systems into real hardware workflows.
Machine LearningRobotics
Responsibilities
Design and implement auto-generation flows that transform control-console specs into structured IR/DSL and then into deterministic firmware + RTL (Verilog/SystemVerilog), including register maps, FSMs, and memory-mapped control/status interfaces
Own digital design correctness end-to-end: clock/reset domains, CDC strategy, timing/constraints, synthesis- and implementation-aware RTL, and timing closure readiness (FPGA and/or ASIC-style flows)
Build and maintain integration layers for common buses and protocols (UART/SPI/I2C/CAN/Ethernet) and internal fabrics (AXI/APB/Wishbone), including clean memory-mapped control/status architectures
Develop verification infrastructure: self-checking testbenches, assertion-based verification (SVA), linting, coverage-driven regression, and formal methods where applicable
Implement tool-driven feedback loops that run synth/sim/formal (e.g., Verilator/ModelSim-class simulators; formal where possible), parse failures deterministically, and automatically propose/patch fixes with clear traceability
Ship CI/CD and regression systems for generated artifacts: golden tests, build determinism, reproducible tool runs, artifact provenance, and 'no silent changes' guardrails
Add safety/security guardrails for generated control logic: invariants, forbidden-state constraints, privilege boundaries, safe default states, audit logging, and policies that prevent unsafe or irreproducible outputs from entering production
Collaborate closely with platform, ML/agent teams, and domain experts to integrate the pipeline into real workflows and hardware programs
Qualification
Required
Strong digital design experience: FSM design, register maps, timing/constraints, clock/reset domain design, CDC fundamentals, and debug in simulation and on hardware
Experience integrating hardware protocols/buses, including memory-mapped control/status patterns and practical bring-up considerations
Solid verification background: self-checking testbenches, SVA/assertions, familiarity with UVM concepts, linting, and comfort using simulation tools (e.g., Verilator and commercial simulators). Formal experience is a plus
Practical understanding of FPGA and/or ASIC flows and what it takes to deliver synthesizable, timing-clean, integration-ready RTL
Proven ability to build reproducible automation pipelines: deterministic codegen, structured interfaces, error parsing/classification, regression testing, and CI/CD
Experience with agentic LLM pipeline engineering: spec → structured IR/DSL, deterministic templating/codegen, tool-calling loops, and robustness/safety mechanisms that keep automated generation correct and auditable
Strong software engineering fundamentals (clean architecture, testing discipline, versioning/provenance, reliability mindset)
Benefits
Meaningful equity
Benefits
Company
Grafton Sciences
Building systems of general physical ability to enable superintelligence
Founded in 2024
11-50 employees
H1B Sponsorship
Grafton Sciences has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2)
Funding
Current Stage
Early StageCompany data provided by crunchbase