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MatX · 13 hours ago

Signal & Power Integrity Engineer

Mountain View, CA

Full-time

Hybrid

Senior Level

5+ years exp

MatX is looking for a motivated Signal & Power Integrity Engineer to join their hardware engineering team to solve cutting-edge technical challenges in high-performance AI chips and systems. In this role, you will design high-speed SerDes channels and power delivery networks to ensure reliable electrical performance for accelerator chips and critical components.

Artificial Intelligence (AI)HardwareManufacturingSemiconductor

No H1B

Responsibilities

Signal Integrity (SI) for interfaces of PCIe 6/7, 224-Gbps PAM4, HBM and D2D

Optimize interconnects from uBump to C4 bump, substrate uvia, and PTH via and PCB via to minimize the insertion loss

Channel Modeling and simulation for interfaces of PCIe 6/7, 224-Gbps PAM4, HBM, D2D based on IP electrical spec and physical design rules

Perform channel analysis using S-parameters, eye-diagram, and BER estimation, insertion loss/crosstalk budgets

Generate physical design rules for interposer LSI, substrate, and PCB layout

Design and simulate PDN (Power Delivery Networks) from VRM to die/package: impedance targets, decoupling strategy, and resonances

Perform frequency-domain impedance and time-domain transient analysis (AC/DC)

Evaluate DC IR drop and transient voltage stability under dynamic loading

Correlate simulation to lab results using VNA, TDR, and oscilloscope measurements

Support bring-up and debug of boards/modules exhibiting SI/PI anomalies

Conduct high-speed SerDes bench BER testing to ensure channel performance

Perform power transient and noise measurements with oscilloscope

Qualification

Signal Integrity (SI)Power Integrity (PI)Channel ModelingHigh-speed interface protocolsAnsys HFSS / SIwaveKeysight ADSCadence ClarityScripting skillsHands-on lab experiencePCB designCrosstalk mitigation

Required

BSEE or MSEE in Electrical Engineering, Applied Physics, or related field

5 - 8 years of experience in SI/PI engineering or related high-speed hardware design

Proficiency with industry tools such as Ansys HFSS / SIwave, Keysight ADS, Cadence Clarity and Sigrity, Keysight PathWave, PowerSI, SPICE, etc

Familiar with PCB design and substrate design, via optimization and modeling

Strong understanding of return-path design, crosstalk mitigation, and PDN target impedance concepts

Hands-on lab experience with oscilloscopes, VNAs, and power measurement equipment

Preferred

Experience with 224 Gb/s interconnects and CoWoS-L interposer design

Scripting skills (Python, MATLAB, TCL) for automation and data processing

Familiarity with high-speed interface protocols (Ethernet/PCIe/HBM) and ability to perform channel analysis based on relevant specifications, such as COM analysis for 224G SerDes

Benefits

Company subsidized Health, Dental, and Vision insurance; Flexible Savings Accounts (FSA), and a Health Savings Account (HSA) with a lump sum company contribution

Choose from Guardian 401K and/or Roth IRA (or both) and receive a 5% company contribution, even if you don’t! Plus 100% paid Life and long-term disability insurances.

4 weeks PTO (accrued), 12 holidays & 3 weeks remote/flexible work per year

100% paid mental health benefit via SpringHealth and Guardian EAP

$1,500 yearly towards conferences, courses, and other learning

Team lunches, quarterly off-sites, and regular town halls

We’ll pay for your commute (up to 1 hr) to get work done during your commute!

$50/month to use on the perks you care about most

Up to 12 weeks of paid parental leave & 10 weeks of pregnancy disability leave, regardless of path to parenthood. Plus Maven reproductive health & parental benefit