Tenstorrent · 1 month ago
Staff Design for Test STA Engineer
Santa Clara, California, United States
Full-time
Onsite
Lead/Staff
$100K/yr - $500K/yrTenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. As a Staff Design for Test STA Engineer, you will be a key technical leader in ensuring the testability, quality, and performance of next-generation AI processors, defining and implementing DFT methodology and collaborating with various engineering teams for silicon success.
AI InfrastructureApplication Specific Integrated Circuit (ASIC)Artificial Intelligence (AI)ElectronicsMachine LearningSemiconductor
No H1B
U.S. Citizen Only
Responsibilities
Coordinate DFT requirements across SOC, IP and product teams and work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure
Lead the definition, generation, and validation of comprehensive DFT timing constraints (SDC) to ensure timing closure for all test modes (e.g., Scan, JTAG, Memory BIST)
Own the STA sign-off for DFT modes at both the block and top-level, including corners and operating conditions, using industry-standard tools (e.g., PrimeTime, Tempus etc)
Work closely with the Physical Design team (Synthesis, P&R) to drive timing convergence, resolve complex timing violations, and generate necessary timing ECOs
Identify and implement improvements to existing DFT and STA flows, enhancing efficiency and robustness
Participate in ATE targeted test patterns, validation and silicon-debug
Work closely with test and product engineering teams on silicon characterization and validation
Qualification
Required
Deep knowledge of core DFT concepts including Scan Compression and insertion, Memory BIST and repair schemes, JTAG/IJTAG, and at-speed test methodologies
Comprehensive understanding of Clock Domain Crossings (CDC), Reset Domain Crossings (RDC), timing sign-off modes and constraints, and proficiency in using industry-leading Static Timing Analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus etc)
Deep knowledge of DFT specific timing modes including JTAG, Scan Shift, Scan Slow Capture, Scan Fast Capture, Memory BIST etc
Experience in Verilog/SystemVerilog RTL coding and back-annotated gate-level verification
Coordinate DFT requirements across SOC, IP and product teams and work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure
Lead the definition, generation, and validation of comprehensive DFT timing constraints (SDC) to ensure timing closure for all test modes (e.g., Scan, JTAG, Memory BIST)
Own the STA sign-off for DFT modes at both the block and top-level, including corners and operating conditions, using industry-standard tools (e.g., PrimeTime, Tempus etc)
Work closely with the Physical Design team (Synthesis, P&R) to drive timing convergence, resolve complex timing violations, and generate necessary timing ECOs
Identify and implement improvements to existing DFT and STA flows, enhancing efficiency and robustness
Participate in ATE targeted test patterns, validation and silicon-debug
Work closely with test and product engineering teams on silicon characterization and validation
Benefits
Highly competitive compensation package and benefits
Company
Tenstorrent
Tenstorrent develops AI hardware and software solutions for data processing and machine learning application.
Founded in 2016
501-1000 employees
Funding
Current Stage
Late StageTotal Funding
$1.03BKey Investors
FidelityEPIQ Capital GroupEclipse Ventures
2024-12-02Series D· $693M
2023-08-02Series Unknown· $100M
2021-05-20Series C· $200M
Leadership Team
Jim Keller
CEO
Keith Witek
Chief Operating Officer
Recent News
2026-01-07
TechRadar.com
2026-01-07
2026-01-06
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