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Samsung Ads · 1 month ago

CPU Micro-Architect

3655 N 1st St, San Jose, CA, USA

Full-time

Onsite

Senior Level, Lead/Staff

$180K/yr - $297K/yr

13+ years exp

Samsung is a world leader in advanced semiconductor technology, focusing on creating a better world through excellence. The CPU Micro-Architect will be responsible for designing and optimizing high-performance CPU microarchitectures for various applications, collaborating with teams to enhance SoC designs and performance evaluation.

Marketing & Advertising

Responsibilities

You design and optimize high-performance CPU microarchitectures for mobile and other applications

You perform quantitative analysis of key mobile benchmarks and correlate with hardware performance monitoring unit (PMU) stats

You develop and implement innovative microarchitecture techniques such as pipelining, caching, prefetching, and branch prediction

You collaborate with cross-functional teams to develop and integrate system-on-chip (SoC) designs

You analyze and optimize CPU performance using top-down microarchitecture analysis methods

You extract and assess key microarchitecture ideas from open literature and apply them to our designs

You write RTL code (Verilog or SV) and C/C++/Python scripts for performance evaluation of microarchitecture techniques

Qualification

CPU microarchitectureRTL coding (Verilog/SV)C/C++/Python scriptingQuantitative analysisSoC designIntegrationHigh-performance computingMachine learning experienceArmv8/v9 ISA knowledgeCommunication skillsCollaboration skills

Required

15+ years of experience with a Bachelor's Degree in Computer Science/Engineering, or 13+ years of experience with a Master's Degree, or 11+ years of experience with a Ph.D

Strong fundamentals in key computer architecture concepts, such as virtual aliasing, pipelining, cache hierarchies, coherency, memory subsystem, etc

Deep knowledge in high-performance OoO CPU microarchitecture and SOTA optimization techniques in key areas such as pipelining, interlock, caching, prefetching, branch prediction, cache/TLB hierarchy and their PPA implications

Ability to perform quantitative analysis of key mobile benchmarks such as Geekbench6 and SPECCPU17 and correlation with HW PMU stats (cache misses, TLB misses, pipeline stalls, etc.)

Extensive programming experience with RTL code (Verilog or SV), and writing C/C++/Python scripts, for performance evaluation of uarch techniques

Working experience with top-down microarchitecture analysis method (based on PMU stats)

Ability to extract and assess key uarch ideas in open literature

Strong communication and collaboration skills, with the ability to work effectively in a cross-functional team environment

Preferred

Actual RTL implementation experience on high-performance OoO processors

Knowledge of system-on-chip (SoC) design and integration

Experience with machine learning and AI accelerators

Working experience of Armv8/v9 ISA and extensions or equivalent (such as x86 and RISCV), particularly in the areas of vector/AI/security/memory safety features (such as Realms, memory tag extension) and their use cases