Efficient Computer · 21 hours ago
Staff Digital Design Engineer
San Jose, CA
Full-time
Onsite
Lead/Staff
$180K/yr - $220K/yr
10+ years expEfficient Computer is developing the world’s most energy-efficient general-purpose computer processor, utilizing patented technology for ultra-low-power performance. As a Staff Digital Design Engineer, you will engage in RTL development, integration, simulation, and silicon implementation of energy-efficient processors, collaborating with various engineering teams to enhance chip design.
ComputerEmbedded SoftwareInformation TechnologyManufacturingSemiconductor
Responsibilities
Front-end Verilog / System Verilog design and integration. Design, document, and implement large functional blocks of design while adhering to the design requirements. Integrate IPs developed in-house and procured from external vendors
Develop a deep understanding of Efficient’s ultra-efficient compute architecture, and make improvements to it using relevant industry experience
Develop and maintain unit-level test cases and debug top-level RTL and netlist simulations
Work with the verification team to review verification plans, debug test case failures, and analyze and review coverage statistics. Assist the verification team with exclusions to meet a 100% coverage goal
Develop module-level and top-level synthesis constraints. Run and review synthesis to check the correctness of constraints. Work with the physical design team to identify and resolve timing issues
Drive best practices in clock/reset-domain (CDC/RDC) verification and linting, building automated checks and reusable methodologies that raise design quality across teams
Define and implement an energy-efficient architecture, partitioning the design into multiple power domains. Own power-domain and sequencing verification by building, automating, and maintaining checks with industry-standard tools and scripts
Estimate power consumption of digital circuits in specific modes and scenarios by using simulation and other industry-standard tools
Be a role model for junior engineers. Mentor and coach junior engineers on design concepts and on the adoption of new tools and methodologies
Qualification
Required
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
10+ years of hands-on experience in front-end digital design and ASIC development across multiple product cycles
Strong understanding of RTL-to-Netlist implementation, DFT concepts, constraint development, synthesis, and static timing analysis
Expertise in running and debugging RTL and gate-level simulations
Proficiency with power-domain partitioning, UPF, and power-aware simulation/debug
Demonstrated experience interpreting reports from and providing waivers for CDC, RDC, and lint checks using industry-standard tools
Knowledge of widely used industry interfaces (e.g., I2C, SPI, I2S, UART, MIPI, HDMI, LVDS, USB, PCIe)
Proficiency with modern development infrastructure: CI pipelines, Git/GitHub workflows, and AI-assisted design/verification tools
Strong familiarity with engineering productivity tools such as Jira (task/sprint tracking) and Confluence (documentation and knowledge sharing)
Excellent teamwork skills and the ability to thrive in a fast-paced, multitasking environment
Preferred
Processor architectures
Low-power design techniques
Analog design and mixed-signal integration
AMS and real-number modeling
FPGA design
Hardware emulation and acceleration platforms
Benefits
401K match
Company-paid benefits
Equity program
Paid parental leave
Flexibility
Company
Efficient Computer
Efficient is creating the world's most energy-efficient general-purpose processor.
11-50 employees
H1B Sponsorship
Efficient Computer has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (5)
2024 (3)
Funding
Current Stage
Early StageTotal Funding
$69.75MKey Investors
Eclipse Ventures
2025-11-18Series Unknown· $53.75M
2023-12-05Seed· $16M
Leadership Team
Brandon Lucia
Co-founder & CEO
Recent News
2025-07-31
Company data provided by crunchbase