Cadence · 7 hours ago
Senior Principal Emulation Design Engineer
San Jose, CA
Full-time
Onsite
Senior Level, Lead/Staff
$154K/yr - $286K/yr
7+ years expCadence is a company focused on technology innovation, and they are seeking a Senior Principal Emulation Design Engineer to lead the development of full system emulation and verification solutions. The role involves working with emulation platforms to develop high-fidelity models and verification environments, ensuring smooth transitions from simulation to emulation while optimizing designs for performance and accuracy.
AerospaceElectronic Design Automation (EDA)HardwareMobileSemiconductorSoftware
Responsibilities
Lead the development and deployment of PHY logic and interface models for emulation platforms including Palladium and Protium
Design, integrate, and validate high-speed interface subsystems (SerDes, chip-to-chip links) in full-system emulation environments
Develop end-to-end verification flows, including:
System-level modeling (microcontrollers, memories, NoC, controllers, MACs)
Custom test case development and automation
Interface performance analysis and validation
Convert Analog/Mixed-Signal (AMS) parallel and serial models into emulation-ready implementations with functional and bit accuracy
Enable bare-metal driver validation and early software stack development in emulation
Collaborate with architecture, IP, verification, and software teams to ensure smooth transitions from simulation to emulation
Optimize multi-clock domain designs for accuracy, performance, area, and runtime
Drive innovation in emulatable IP and AVIP solutions, influencing next-generation verification methodologies
Support system prototyping and early bring-up for complex SoC designs
Qualification
Required
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
7–15 years of experience in system-level design, verification, or emulation
Strong experience with high-speed communication protocols, including: PCIe, UCIe, Ethernet, UALink, DDR, USB, SPI, JTAG, AMBA
Proven Expertise In: SystemVerilog for synthesizable RTL design
C and Python for modeling, scripting, automation, and test development
Converting AMS designs into emulation models supporting configuration, control, and status monitoring
Lab debug, performance analysis, and test case development
Hands-on experience with emulation and prototyping platforms, such as: Palladium, Protium, Zebu, HAPS, Veloce, FPGA
Strong understanding of verification flows, emulation acceleration, and hardware/software co-verification
Preferred
Experience building Acceleratable Verification IP (AVIP)
Familiarity with end-to-end verification environments from simulation through emulation
Background in system prototyping, SoC bring-up, and pre-silicon validation
Strong analytical, debugging, and problem-solving skills
Excellent communication, collaboration, and technical leadership abilities
Benefits
Paid vacation and paid holidays
401(k) plan with employer match
Employee stock purchase plan
A variety of medical, dental and vision plan options
And more
Company
Cadence
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems.
10001+ employees
H1B Sponsorship
Cadence has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (252)
2024 (221)
2023 (282)
2022 (330)
2021 (233)
2020 (209)
Funding
Current Stage
Public CompanyTotal Funding
unknown1998-02-20IPO
Leadership Team
Paul Cunningham
Senior Vice President and General Manager
Tom Beckley
Senior Vice President, Custom IC & PCB Group
Recent News
eeNews Europe
2025-12-26
Company data provided by crunchbase