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Marvell Technology · 1 week ago

Senior Staff Post-Silicon Validation Engineer, High Speed SERDES

Santa Clara, CA

Full-time

Onsite

Senior Level, Lead/Staff

$121K/yr - $182K/yr

5+ years exp

Marvell Technology is a leader in semiconductor solutions that drive data infrastructure across various industries. As a Senior Staff Post-Silicon Validation Engineer, you will manage PHY IP Validation, conduct silicon bring-up, and perform high-speed signal validation while collaborating with cross-functional teams to resolve technical issues.

DSPInternet of ThingsManufacturingSemiconductorWireless

Growth Opportunities

No H1B

U.S. Citizen Only

Responsibilities

Manage PHY IP Validation in post-silicon environment including defining, documenting, executing, and reporting the overall PHY validation/test plan for Marvell storage devices

Conduct lab-based silicon bring-up and unit test execution focused on PCIe Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the PCIe stack

Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER. Analyze and debug issues on PHY protocol of storage interface (SATA, SAS, PCIe, Ethernet)

Troubleshoot failing tests using diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers

Lead collaborative technical discussions to drive resolution on technical issues

Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to PHY IPs

Partner effectively with customers to address design issue and debug failure

Qualification

High-speed SERDESPCIe protocolsHigh Speed IO testingTest equipment for SERDESBoard design knowledgeAnalytical skillsPerlPythonProblem-solving skillsCommunication skills