OLIX · 1 week ago
Senior/Staff Digital Design Engineer
Austin, CO
Full-time
Onsite
Senior Level, Lead/Staff
$170K/yr - $285K/yr
7+ years expOLIX is at the forefront of AI technology, developing the Optical Tensor Processing Unit (OTPU) to address the growing infrastructure gap in chip and power station production. They are seeking skilled Senior/Staff Digital Design Engineers to own the digital design of high-speed silicon, focusing on CMOS digital design and collaboration across multidisciplinary teams.
Semiconductors
Responsibilities
Architect, design and implement high‑throughput digital pipelines (multi‑GSPS input rate, continuous streaming data paths, deep pipelining and hand‑shaking) in advanced CMOS nodes
Prototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent): bring‑up real‑time demos, exercise high‑speed transceivers, and feed learnings back into the ASIC
Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gate‑level sign‑off
Own RTL development (SystemVerilog / Verilog / VHDL) including synthesis, static‑timing closure, formal and constrained‑random verification
Analyse power, performance and area (PPA); implement innovative techniques to achieve aggressive bandwidth‑per‑watt targets
Collaborate with optical‑hardware, mixed‑signal and software teams to optimise data‑converter interfaces, clock‑domain crossings and firmware abstractions
Mentor junior engineers, lead design reviews and champion best‑practice design methodologies
Qualification
Required
7+ years of hands-on digital design for high-performance ASICs or SoCs, including ownership of at least one product that processes a continuous real-time data stream
Proven success closing timing on multi-hundred-MHz to multi-GHz clock domains and integrating high-speed IP (e.g., SerDes, HBM/DDR, PCIe, 100 GbE or similar)
Expertise with industry-standard EDA flows: RTL synthesis, CDC/RDC, STA, power-intent (UPF/CPF), lint, and gate-level simulation
Demonstrated FPGA prototyping skills: constraint management, transceiver tuning, and hardware debug in the lab
Proficiency using MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed-point analysis and test-vector generation
Solid grounding in digital signal-processing concepts, computer-architecture fundamentals and semiconductor device physics
Excellent communication and cross-functional collaboration abilities; thrives in a fast-moving, ambiguous environment
Architect, design and implement high-throughput digital pipelines (multi-GSPS input rate, continuous streaming data paths, deep pipelining and hand-shaking) in advanced CMOS nodes
Prototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent): bring-up real-time demos, exercise high-speed transceivers, and feed learnings back into the ASIC
Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gate-level sign-off
Own RTL development (SystemVerilog / Verilog / VHDL) including synthesis, static-timing closure, formal and constrained-random verification
Analyse power, performance and area (PPA); implement innovative techniques to achieve aggressive bandwidth-per-watt targets
Collaborate with optical-hardware, mixed-signal and software teams to optimise data-converter interfaces, clock-domain crossings and firmware abstractions
Mentor junior engineers, lead design reviews and champion best-practice design methodologies
Preferred
Tape-out experience at 22 nm or below
Knowledge of coherent optical links or photonic-electronic co-design
Familiarity with AI/ML workloads, systolic arrays or tensor-processing architectures
Contributions to open-source RTL, verification frameworks or FPGA boards
Benefits
Equity & Ownership: Meaningful stock options. You’re not just joining the mission; you’re owning a piece of it.
$36k annual Living-Local Bonus if your residence is within 20 minutes of the office.
Healthcare Coverage: Multiple high-quality medical plan options, including family coverage.
Health Savings Account: A high-deductible medical option with a company-funded health savings account (HSA).
Dental & Vision: Dental and vision coverage.
Additional Coverage: Life insurance, plus short- and long-term disability.
Wellbeing Support: Mental health resources, fertility and family-building support.
Commuter Benefits: Pre-tax commuter and parking benefits.
401(k): Access to a 401(k) retirement plan with a 4% employer match, with both traditional and Roth contribution options.
Company
OLIX
OLIX is building the infrastructure for Frontier AI. (Formerly operating as Flux)
51-200 employees
Funding
Current Stage
Growth StageCompany data provided by crunchbase