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Flux Computing · 11 hours ago

Senior / Staff Digital Design Engineer

Austin, TX

Full-time

Onsite

Senior Level, Lead/Staff

$194K/yr - $270K/yr

7+ years exp

Flux Computing is seeking highly skilled and motivated Senior/Staff Digital Design Engineers with a strong focus on CMOS digital design. The role involves taking end-to-end ownership of high-speed, real-time data-processing silicon, from early algorithm modeling to verified RTL and silicon bring-up, while collaborating with multidisciplinary teams to create next-generation OTPUs.

Artificial Intelligence (AI)HardwareMachine LearningManufacturingOptical Communication

H1B Sponsored

Responsibilities

Architect, design and implement high‑throughput digital pipelines (multi‑GSPS input rate, continuous streaming data paths, deep pipelining and hand‑shaking) in advanced CMOS nodes

Prototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent): bring‑up real‑time demos, exercise high‑speed transceivers, and feed learnings back into the ASIC

Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gate‑level sign‑off

Own RTL development (SystemVerilog / Verilog / VHDL) including synthesis, static‑timing closure, formal and constrained‑random verification

Analyse power, performance and area (PPA); implement innovative techniques to achieve aggressive bandwidth‑per‑watt targets

Collaborate with optical‑hardware, mixed‑signal and software teams to optimise data‑converter interfaces, clock‑domain crossings and firmware abstractions

Mentor junior engineers, lead design reviews and champion best‑practice design methodologies

Qualification

CMOS digital designRTL developmentFPGA prototypingAlgorithm modellingDigital signal processingEDA flowsHigh-speed IP integrationCommunication skillsCross-functional collaborationMentoring

Required

7+ years of hands-on digital design for high-performance ASICs or SoCs, including ownership of at least one product that processes a continuous real-time data stream

Proven success closing timing on multi-hundred-MHz to multi-GHz clock domains and integrating high-speed IP (e.g., SerDes, HBM/DDR, PCIe, 100 GbE or similar)

Expertise with industry-standard EDA flows: RTL synthesis, CDC/RDC, STA, power-intent (UPF/CPF), lint, and gate-level simulation

Demonstrated FPGA prototyping skills: constraint management, transceiver tuning, and hardware debug in the lab

Proficiency using MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed-point analysis and test-vector generation

Solid grounding in digital signal-processing concepts, computer-architecture fundamentals and semiconductor device physics

Excellent communication and cross-functional collaboration abilities; thrives in a fast-moving, ambiguous environment

Architect, design and implement high-throughput digital pipelines (multi-GSPS input rate, continuous streaming data paths, deep pipelining and hand-shaking) in advanced CMOS nodes

Prototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent): bring-up real-time demos, exercise high-speed transceivers, and feed learnings back into the ASIC

Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gate-level sign-off

Own RTL development (SystemVerilog / Verilog / VHDL) including synthesis, static-timing closure, formal and constrained-random verification

Analyse power, performance and area (PPA); implement innovative techniques to achieve aggressive bandwidth-per-watt targets

Collaborate with optical-hardware, mixed-signal and software teams to optimise data-converter interfaces, clock-domain crossings and firmware abstractions

Mentor junior engineers, lead design reviews and champion best-practice design methodologies

Preferred

Tape-out experience at 22 nm or below

Knowledge of coherent optical links or photonic-electronic co-design

Familiarity with AI/ML workloads, systolic arrays or tensor-processing architectures

Contributions to open-source RTL, verification frameworks or FPGA boards

Benefits

Competitive stock options, you’re not just part of the journey, you will own a piece of it.

We offer financial and operational relocation support (US and abroad), through a dedicated third-party provider who is on hand to make your move to Austin as seamless as possible.

We offer visa sponsorship so if we make you an offer we will make every reasonable effort to secure you a visa, but we may not be able to sponsor visas for every role and candidate.

We’re in the process of setting up a US group policy once we have 5+ employees. In the meantime, we’re providing a health insurance stipend of $800/month to offset costs. Once the group policy is live, Flux will cover 100% of the employee premium, and offer options like dental, vision and life insurance with an aim to remain competitive among Austin tech and start up employers.

We offer US employees access to a 401(k) retirement savings plan and we plan to introduce an employer match in line with Austin tech market norms (commonly in the 4-5% range). Our goal is to keep our retirement benefits competitive while we scale.

Top of the line, high-spec tech for everyone.

Sony noise-cancelling headphones and ergonomic setups to keep you comfortable and focused.

Personal company card to spend on tools that help you do your job - like ChatGPT Pro or anything else that boosts your workflow.

Periodic travel to London HQ and regular team socials.

33 days of paid time off (PTO), including US federal holidays.