Astera Labs · 4 weeks ago
Senior System Validation Engineer – SerDes/Ethernet (PAM4)
San Jose, CA
Full-time
Onsite
Senior Level
6+ years expAstera Labs is a company that provides rack-scale AI infrastructure through purpose-built connectivity solutions. The Senior System Validation Engineer will develop and perform system validation tests for Data Center equipment, ensuring product conformance to high performance and functionality requirements for AI and Machine Learning applications.
AutomotiveElectronicsIntelligent SystemsSemiconductor
Responsibilities
Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms
Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications
Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion
Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions
Qualification
Required
Strong academic and technical background in electrical or computer engineering
At minimum, a Bachelor's is required
≥6 years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications
Preferred
Master's degree
Strong knowledge in scripting for automation of validation efforts (e.g. Python, Matlab)
Experience with silicon bring-up, debugging complex electrical and system performance issues, production ramp
Very knowledgeable about common high-speed SerDes protocols like Ethernet, PCIe etc., and the electrical, system level specifications defined in the standard documents (IEEE802.3, PCIe Base Specification etc.)
Very knowledgeable about SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget
Experience working with lab equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes and VNA
Experience with PAM4 SerDes validation (200G/100G/50G)
Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc
Knowledge of Signal Integrity simulation tools
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision
Entrepreneurial, open-mind behavior and can-do attitude
Company
Astera Labs
Astera Labs is a semiconductor company that provides connectivity solutions for intelligent systems.
201-500 employees
H1B Sponsorship
Astera Labs has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (50)
2024 (44)
2023 (17)
2022 (26)
2021 (14)
2020 (7)
Funding
Current Stage
Public CompanyTotal Funding
$206.35MKey Investors
Fidelity
2024-03-20IPO
2022-11-17Series D· $150M
2021-09-27Series C· $50M
Leadership Team
Jitendra Mohan
CEO
Casey Morrison
Chief Product Officer, Co-Founder
Recent News
The Motley Fool
2026-01-07
2025-12-29
Company data provided by crunchbase